     
     ----------------------------------------
     |  Final Release Notes for 296SA RISM  |
     ----------------------------------------

************************************************************
*** RISM V2 enhancements and fixes placed in the public  ***
***     domain by ChipTools Inc.                         ***
***                                                      ***
*** RISM enhancements for 296SA placed in the public     ***
***     domain by Intel Corp.                            ***
***                                                      ***
***      THIS SOFTWARE IS NOT A SUPPORTED PRODUCT.       ***
************************************************************

Disclaimer
----------------------------
This files contains details regarding RISM source code that is not
shipped in the first relase of the 80296SA Evaluation Board kit.
The listing file for RISM (sar_main.lst) is included to provide 
insight into how the board is operating during any given command.
However, due to support issues, the source code itself will not
be publicly released.  


<<<<< Modifications -  09/06/96  C. Tynes >>>>>

RISM Modifications - Version 2.1.02.00
-------------------------------------------
   The following modifications were made to RISM Version 2.0
introduced by ChipTools Inc. in order to support the 296SA
part.  There are very specific modifications for the SA which
will not work with other boards; however, the PC interface 
remains intact with 2 additional commands added to support
flash programming.  The new rism files have all been renamed to 
start with "SAR_*" which represents that these files have been
modified from the ver 2.0 to support the EA Rism specifically.
This version is designed to only work with ECM96EA v1.2.

 1.)  A new bit was defined for the RISM_STAT variable.  Bit #7
      now represents whether flash programming is supported.
      This bit is determined by the setting of FLASH_CMD_ACTIVE.
      This bit was added to allow support for RISM that is running
      from a flash boot block.  Because you can not program flash
      while running in flash, support is required to maneuver RISM
      around in memory to allow the programming of flash memory.
      If this bit is set, the rism will move itself to a ram 
      location during flash programming and return itself to flash
      when it is finished.

 2.)  Two new commands were added to support the above modification.
          SET_FLASH_FLAG     =  0x1B
          SET_FLASH_FLAG_OFF =  0x1C
      Upon receipt of a set_flash_flag command, rism will move itself
      up into page FF to allow programming of the flash.  If it gets
      a set_flash_flag_off, it will return rism to running from flash.

 3.)  An additional configuration file was added, SAR_SCFG.ASM, to 
      set aside specialized Chip Select settings required by the SA.
      This file manipulates the interrupt vectors that are required 
      to be in page FF to jump to reserved locations ( 0FF0070-0FF007F )
      and hard codes ejmps back into the flash boot block in page 08
      to the appropriate handlers.  IMPORTANT:  If any code modifications
      move the NMI or TRAP handlers, those hardcoded ejmps will
      have to be calculated and fixed manually.

 4.)  A lot of extraneous IF..ELSE..ENDIF code was removed by pulling
      out the MODEL_KC option that is in the RISM v2.0.

 5.)  A few miscellaneous registers that could not be run in windows
      were modified to use the full address.

 6.)  Enabled NMI interrupt to handle UART interrupts and disabled the 
      RI interrupt.

 7.)  Added RISMREV_ID to the monitor escape table.  This will provide
      the ability for versions, sub-versions, revisions, and sub-revisions.
      The idea is to provide a way to identify the set of interface commands
      provided and a way to distinguish the implementation of the interface.
      (C.Tynes)

<<<<< Modifications -  09/13/96  C. Tynes >>>>>

RISM Version 2.1.03.00

  8.) Modified the way RISM calculates offsets for the BAUD_REG_TABLE and
      the MONITOR_ESC_TABLE to coincide with the lookup in page 0FH instead
      of the default FFH.  Also changed the SET_BAUD handler back to 
      original setting of allowing any number less than 7 to do a lookup
      in the BAD_REG_TABLE for the appropriate baud value setting.
      [ NOTE:  THIS MODIFICATION REQUIRES ECM96SA v1.3 TO FUNCTION PROPERLY 
        WITH THE NEW BAUD RATE CALCULATIONS.  CONTACT TOOL VENDOR FOR UPGRADE
        SEQUENCE IF REQUIRED. ]

<<<<< Modifications -  12/12/96  C. Tynes >>>>>

RISM Version 2.1.05.01

  9.) Modified the DTR_ACTIVE variable to represent the correct configuration
      of the board since the DTR line is connected to the NMI line.  This
      will also allow interrupts to be disabled for single-step debugging of
      some instructions.

 10.) A RESET_FLAG big has been added to the RISM_STAT variable at bit
      position 5.  This bit is cleared upon board reset and can be used to 
      determine when a board reset happens.  This can be accomplished through  
      the MONITOR_ESCAPE features by sending it a value of #0F3B4h (as 
      opposed to a 1 for reset) which will set the RESET_FLAG bit to 1 (one).
      By checking the RISM_STAT variable, you can determine if the board is reset
      when the value becomes 0 (zero).  The value, 0F3B4h, was chosen as a
      complex sequence to prevent accidental reset of the RESET_FLAG bit.

 11.) The Version & Revision IDs are copied to page FF along with the Device ID
      and Frequency variables.

 12.) All modifications to READ & WRITE commands related to the accumlator bug
      in the earlier releases.  (Special thanks to Ken Anderson, ChipTools Inc.)


296SA Embedded Controller Monitor v1.2 (ECM96SA)
-------------------------------------------------
Almost all releases of ECM96 only support on-chip uarts and their distinct
way of changing baud rates.  RISM can handle setting baud rates based on a 
table of information in the RISM data space.  However, the 296SA eval board
uses a 1.8432 Mhz clock for the uart which uses baud values that overlap
the baud rate table (i.e. 38400 = 3 baud value).  To support changing baud
rates on the fly along with the newer RISM commands, a decision was made to
modify ECM96EA.EXE (from the 196EA release) to support off-chip uarts.  The
end product is ECM96SA.EXE which is included on this disk.  It supports every
function, including booting from flash & programming flash, that the 196EA
rism and ecm did.  Details of this will be found in the 296SA Eval Board manual.
Remember, ECM96SA.EXE is not a supported product but has been tested and is
currently being used by many types of engineers for silicon evaluation.  

<<<<< Modifications -  09/13/96  C. Tynes >>>>>

Version 1.3 - Modified the set_baud_board function to increase the baud
              rate based on the rism baud_rate_table index instead of
              attempting to calculate the rate itself.  This was designed
              to work with RISM v2.1.03 and later.


