
Copyright (C), 1994-2003 Aware Inc. All Rights Reserved.
Aware DMT Technology. Proprietary and Confidential.


                 **************************************************
                 *                  RELEASE NOTES                 *
                 **************************************************


FILE:            HWEngineLib6.2_release_notes.txt

DESCRIPTION:     This file contains information about each release up to the most current
                 release. Each release is clearly delineated below with its respective
                 date and contact person.

                 Please report all bugs and suggestions for improvement to the contact
                 person listed for the most-recent release.

ADDRESS:         40 Middlesex Turnpike, Bedford, MA 01730-1413 USA
TELEPHONE:       781.276.4000
FAX:             781.276.4001
WEB:             http://www.aware.com

==========================================================================================
(09/17/08 Wei Wu) (After Checkpoint)
==========================================================================================
Highlights:
-----------
Fixed a bug in Zephyr initialization.

Details:
-----------
1. ROW_WIDTH is defined by (D - M - 1 + 2*FIFO_EXT). Since FIFO_EXT = 1, ROW_WIDTH = D - M + 1.
In current code, it is calculated by D + M + 1, which is wrong.
2. We will have 65KB de/interleaver buffer memory. Therefore, we divide it into two 32.5KB blocks
for ILVB and DILVB.

Files:
-----------
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL1.c (1)
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL2.c (2)
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL1.c (1)
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL2.c (2)

==========================================================================================
(08/25/08 Wei Wu) (After Checkpoint)
==========================================================================================
Highlights:
-----------
Enable CPE build for VDSL_61.

Details:
-----------
1. For VDSL_61, DisablePrbsGen() is used in both CO and CPE builds.
2. Initialize IFFT zero range registers for CPE before the bandplan is known. It is updated
after we get the bandplan information from CO.
3. Disable LUT error check. For CPE builds, we don't have enough memory to store FDQ coefficients
so an LUT error will always appear. For now, we ignore such errors.
4. When setting Rx tone offset, write to both QTP PRBS and QT RTV registers.
5. Enable Rx descrabling by setting QTP PRBS generation bit.
6. In SwitchTXPingPongTable, only set active address register when number of tones used is larger
than 0.
7. Copy function ConfigTxNumTone() from HWEngine5.0. This function is only used by CPE.
8. In StartTxDataPath(), also call DisablePrbsGen() for CPE. This will turn off PRBS generation
when we are in showtime.
9. Update HWEngineLib_61.dsp

Files:
-----------
\Modem\source\HWEngine_62\include\IRI_Iof.h (1)
\Modem\source\HWEngine_61\IRI_Ini.c (2)
\Modem\source\HWEngine_61\IRI_IOf.c (3,4,5,6)
\Modem\source\HWEngine_61\IRI_IOf_train.c (1,7)
\Modem\source\HWEngine_61\show_iof.c (8)

==========================================================================================
(08/22/08 Vivek Goel)
==========================================================================================
Highlights:
-----------
Updated the Zephyr-ILV Rx register configuration as per the latest specification.

Files:
-----------
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL1.c
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL2.c
==========================================================================================
==========================================================================================
(08/08/08 Vivek Goel)
==========================================================================================
Highlights:
-----------
Updated the Zephyr-ILV Tx register configuration as per the latest specification.

Files:
-----------
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL1.c
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL2.c
==========================================================================================
==========================================================================================
(08/01/08 Wei Wu)
==========================================================================================
Highlights:
-----------
Enable HW based SNR calculation during training.

Details:
-----------
1. Added HWEngine function ConfigRTVBuf0_ERR_ACC_OUT_train(), to enable HW noise accumulation.
2. In IridiaControlCommon(), load proper function if RtvSelect is ERR_ACC_OUT

Files:
-----------
\Modem\source\HWEngine_62\include\IRI_Iof.h (1)
\Modem\source\HWEngine_61\IRI_IOf.c (2)
\Modem\source\HWEngine_61\IRI_IOf_train.c (1)

==========================================================================================
(07/31/08 Wei Wu)
==========================================================================================
Highlights:
-----------
Fix bug in sync frame capture.

Details:
-----------
1. We don't need to disable PRBS latch after entering showtime. Disabling tone derotation
is sufficient.
2. Turn on tone derotation when capturing the sync frame.
3. During sync frame transmission, only QTP PRBS is needed. QT PRBS engine is disabled when
QT TOT_DIS=1. Therefore, there is no need to configure them for sync frame Tx.
4. TOT_DIS in QTP register only works for tablecopy functions. Don't set/reset this bit if
tablecopy is not involved.
5. When setting Rx tone offset, configure both QTP PRBS offset and QT RTV0/1 offset.
6. In EnableRxDescrambling(), set QTP PRBS engine bit.

Files:
-----------
\Modem\source\HWEngine_61\show_iof.c (1)
\Modem\source\HWEngine_61\show_iof_VDSL2.c (2,3,4)
\Modem\source\HWEngine_61\IRI_IOf.c (5,6)

==========================================================================================
(07/24/08 Wei Wu)
==========================================================================================
Highlights:
-----------
Another bug fix for dual latency links.

Details:
-----------
According to the spec, we should use longword offset address for ZIR_DTB_RD_START and
ZIT_DTB_WR_START registers. Therefore, we only need to right shift by two bits in initialization.

Files:
-----------
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL1.c
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL1.c
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL2.c
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL2.c

==========================================================================================
(07/23/08 Wei Wu)
==========================================================================================
Highlights:
-----------
Fix bug in Tx/Rx data pump setup for VDSL1. This fix will pass vdsl1_lpbk_test 1 and 2.

Details:
-----------
1. Configure starting location of INLV path to closest longword address after FAST path.
(both Tx and Rx).
2. Add comment about rounding to longword address

Files:
-----------
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL1.c (1,2)
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL1.c (1,2)
\Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL2.c (2)
\Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL2.c (2)

==========================================================================================
(07/16/08 Wei Wu)  (After Checkpoint)
==========================================================================================
Highlights:
-----------
Make necessary changes to enable FDConn VDSL1 training test, FDConn VDSL1/2 Ghs tests.

Details:
-----------
1. Add function DisableLoadTonesToIfftBuf() to disable DCI.
2. The active EGT address in 6.1 is different from active BGTN table. Use the right function
to retrieve the pointer to the EGT.
3. In LoadTxPRBSMsgBytes(), disable DCI too.
4. Use DCI to write to IFFT buffer in LoadSingleToneToIfftBuf() and LoadGhsTonesToIfftBuf().
We always use the end of the active BGTN (address 3483 - 3488 for VDSL).

Files:
-----------
\Modem\source\HWEngine_62\include\IRI_Iof.h (1)
\Modem\source\HWEngine_61\IRI_Ini.c (2)
\Modem\source\HWEngine_61\IRI_IOf.c (3)
\Modem\source\HWEngine_61\IRI_IOf_FFT.c (1,4)

==========================================================================================
(07/03/08 Wei Wu)
==========================================================================================
Highlights:
-----------
Make necessary changes to enable FDConn training test.

Details:
-----------
1. Add three new functions
     ConfigRTVBuf0_FFT_OUT_train()
     ConfigRTVBuf0_SFDQ_OUT_train()
     ConfigRTVBuf0_ERR_OUT_train()
to configure RTV0 during training.
2. Add function IridiaControlCommon() to load proper RTV configuration functions according
to gs_RtvSelect's change.
3. Add LUT initialization in at link start after band plan information is known.
4. Only write to RTV0 (512 tones) during training.
5. Fill inactive gain value at link start.
6. Write IFFT zero ranges at link start after band plan information is known.
7. Fix the address to write/read FDQ coefficients.
8. Check LUT error every time read from or write to HW FDQ memories.
9. Always write to QT RTV offsets directly when set Rx tone offset.
10. Always read from RTV0 in GetRxTones(). Showtime updates will use other HWEngine functions.
11. Preserve PRBS bit information when write to QTP_REG_TX_CTRL.
12. Set proper table copy direction when we switch table.
13. Use SetCoreReg instead of WriteCoreReg in order not to clear irrelevant bits.
14. ConfigRTVBuf0_FFT_OUT(), ConfigRTVBuf0_SFDQ_OUT(), ConfigRTVBuf0_ERR_OUT(), are no longer used.
They are replaced by training functions described in point 1.
15. Disable PRBS machine at the start of showtime (in StartTxDataPath()).
16. Disable PRBS state latching at the start of showtime (in StartRxDataPath()).
17. Specify active table tone ranges when doing an active to inactive table copy.

Files:
-----------
\Modem\source\HWEngine_62\include\IRI_Iof.h (1,2)
\Modem\source\HWEngine_61\IRI_Ini.c (3,4,5,6)
\Modem\source\HWEngine_61\IRI_IOf.c (2,7,8,9,10,11,12,13)
\Modem\source\HWEngine_61\IRI_IOF_mfdq.c (13)
\Modem\source\HWEngine_61\IRI_IOF_train.c (1,13,14)
\Modem\source\HWEngine_61\show_iof.c (15,16)
\Modem\source\HWEngine_61\show_iof_VDSL2.c (13,17)

=======================================================================================
(06/25/08 John Greszczuk)
==========================================================================================

Highlights : Add Support for HW based SNR and FDQ.


Details.
1) RTV control changes
   RTV0 is used for error power accummultion, size 512.
   RTV1 is used to capture the synch frame (size 16). The variable guc_SNRFDQControl which
   was added by the rev2 FW is used to control whether FW or HW updates are done. Only the
   normal FDQ update mode is supported ( not Async).

 SetUpRTVForDDSnrFdqHandler: guc_SNRFDQControl controls the set up RTV buffer for HW or FW based SNR/FDQ
 SetUpRTVForRxSynchFrame: cAPTURE SYNCH FRAME in RTV1.
 ReadRxSynchFrame: Use RTV1.

2) New functions for Iridia control
ResetNoisePowerBuffer   Clears the RTV accumulator buffer
TriggerNoisePowerAcc Sets the NoisePower Control for Power accumulation mode.
TriggerVectorPower   Sets the VectorPower block for calculating the power of the FFT output in the RD_RNG0
DeTriggerVectorPower Clears Vector Power Mode.
ReadVectorPower      Reads and combines the Low and High words of the Vector Power and divides by 2^13.
ReadAccumulatedNoise This routine reads the low and high words of the Accumulated Noise Power per tone.
void EnableFDQ    Enables the HW based FDQ adaptation.
void DisableFDQ      Disables the HW based FDQ adaptation.

3) SwitchTxPingPong() : Set gs_TxNumTones when writing to the QTP_TX_CTRL register.

Files:
   \Modem\source\HWEngine_61\ddsnrfdq_iof.c     (1,2)
   \Modem\source\HWEngine_61\Show_iof_VDSL2.c      (1)
   \Modem\source\HWEngine_61\IRI_IOf.c          (3)


=======================================================================================
(06/12/08 Radha)
==========================================================================================

Highlights : In VDSL1, LP1 should have FAST data and LP0 should have interleave data, but the function seems to be doing the opposite.
            without this switching, fifo_depth is zero, resulting in division by zero exception conditions  in Zep_ILV routines

   Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL1.c
   Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL1.c

=======================================================================================
(06/3/08 Radha)
==========================================================================================

Highlights :

 Task :Integration of FT, FTB 6.1 BMs into ModemHWEngine6.1 workspace and testing of Zephyr and QT loopback tests.

 1. FT6.1 doesn't have strymon related interface logic such as CP, Cs, window generation etc, many files need to be modifed
    to remove any references to those registers. In addition, bit positions for FFT / IFFT/ PARR enable signals are different.
    Also, shadow registers need to be set to proper values as hardware takes inputs from shadowregisters.

2.  FT, FTB buffers reading / writing has been modiifed to byte access.

3.  Previously defined macros for integrating BM5.0 FT such as BMTEST and BM_50 are removed


   \Modem\source\HWEngine_61\afeif_iof.c    (1)
   \Modem\source\HWEngine_61\cri_ini.c      (1)
   \Modem\source\HWEngine_61\DecAdapt_IOf.c    (1)
   \Modem\source\HWEngine_61\EnableParr.c      (1)
   \Modem\source\HWEngine_61\InsertCE.c    (1)
   \Modem\source\HWEngine_61\interrupt_control.c     (1)

   \Modem\source\HWEngine_61\IRI_Ini.c    (1)
   \Modem\source\HWEngine_61\IRI_IOf.c    (1)

   Modem\source\HWEngine_61\IRI_IOf_FFT.c  (1)
   Modem\source\HWEngine_61\IRI_IOf_train.c (1)
   Modem\source\HWEngine_61\IRI_sync.c     (1)
   Modem\source\HWEngine_61\LoadIridiaTransmitGains.c (1)

   Modem\source\HWEngine_61\LoadParrParms.c  (1)
   Modem\source\HWEngine_61\show_lpbk_iof.c (1)



   Modem\source\VDSL_Platform_61\LL_IOF.c   (2)

   VDSL\Bm_6.1\corexec\Source\corexec.c (3)
   VDSL\Bm_6.1\corexec\Source\InitBM.c (3)
   VDSL\Bm_6.1\cri\Source\cri.c       (3)

=======================================================================================
(05/12/08 Vivek Goel)
==========================================================================================

Highlights :
Added code to configure the new global registers added to the Zephyr-ILV BM.

   Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL1.c
   Modem\source\HWEngine_61\RxDataPumpSetUp_VDSL2.c
   Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL1.c
   Modem\source\HWEngine_61\TxDataPumpSetUp_VDSL2.c

=======================================================================================
(04/23/08 Radha)
==========================================================================================

Highlights :

1. Splitting NoiseAcc buffer into NOISeAcc_LSW and NoiseAcc_MSW words in the QT to avoid holes for 2 / 4 port processing

   Modem\source\HWEngine_61\IRI_IOF.c
   Modem\source\HWEngine_61\IRI_Iof_mfdq.c
   Modem\source\HWEngine_61\show_iof.c
   Modem\source\HWEngine_61\show_iof_VDSL2.c

   Modem\source\VDSL_Platform_61\LL_IOF.c

=======================================================================================
(04/18/08 Radha)
==========================================================================================

Highlights :

1. QT running is enabled with the condition of Tx/ Rx enable bits of the selected ports.

   Modem\source\HWEngine_61\IRI_Ini.c  (1)


=======================================================================================
(04/17/08 Radha)
==========================================================================================

Highlights :

1. Removal of LP2 paths in QT. LP order is set to VDSL mode.

2. Modiifcation of data storage in NPR buffer.
   RTV data is written in consecutive locations and MSWord of Noise accumulator is stored in the upper half of NoiseAcc buffer.

3. for TCM, 1bit reordering bit in QTP registers need to be set to 1.

4. 64bit accessing function for the RTV reads is removed.

Modified files :

   Modem\source\HWEngine_61\IRI_Ini.c  (1,2)
   Modem\source\HWEngine_61\IRI_IOF.c  (1,2)
   Modem\source\HWEngine_61\IRI_Iof_mfdq.c  (1,2)
   Modem\source\HWEngine_61\RxDataPumpSetup.c   (1,2)
   Modem\source\HWEngine_61\TxDataPumpSetup.c   (1,2)

   Modem\source\HWEngine_61\show_iof.c  (3)
   Modem\source\HWEngine_61\show_iof_VDSL2.c  (3)

   Modem\source\VDSL_Platform_61\LL_IOF.c   (4)






=========================================================================================
(04/15/08 John )
==========================================================================================

Highlights :

1. Correct the alignment of tone pairs in TCM mode.

Details: With the new QT there must be an even number of 2D symbols in TCM mode. So the starting location of the
QT active table must be set to ensure that there are an appropriate number of tones. In the TX direction
an extra unloaded tone is added if needed. In the Rx direction only the minimum number of zero bit tones are processed to
make the pairs line up.

ie. IF the bat contains [0,0, ... 0 , 2 ,3 4 ] Then the start address is set to the last zero so that the pairing is
( 0 , 2) and (3, 4 ).

2. add comment


Modified files :


   Modem\source\HWEngine_61\IRI_IOF.c        (1)
   Modem\source\HWEngine_61\RxDataPumpSetup.c   (1)
   Modem\source\HWEngine_61\TxDataPumpSetup.c   (1)
   Modem\source\HWEngine_61\IRI_Ini.c        (2)

=========================================================================================
(04/11/08 Radha)
==========================================================================================

Highlights :

1. As RTV is combined with noiseAcc, each tone data occupies 8 bytes.
   In RTV mode, 4 bytes are used for storing real and Imag values and another 4 are empty.
    In noiseAcc mode, all 6 bytes are used. New, 64 bit QT read function is created for accessing Noiseacc/RTV data

2. As same buffer is used for RTV0, RTV1, RTV1 is presently configured to start from
   RTV address + RTV0_count * 8 bytes. In firmware, RTV count is set to 512 ( MAX_RTV_COUNT).
   This parameter may need to be changed in future.

Modified files :

   Modem\source\HWEngine_61\IRI_Ini.c  (1,2)
   Modem\source\HWEngine_61\IRI_IOF.c  (1,2)
   Modem\source\HWEngine_61\IRI_Iof_mfdq.c  (1,2)
   Modem\source\HWEngine_61\show_iof.c  (1,2)

   Modem\source\VDSL_Platform_61\LL_IOF.c   (1)
   Modem\source\VDSL_Platform_\LL_IOF.h   (1)


=========================================================================================
(04/09/08 John Greszczuk and Vivek)
==========================================================================================

Highlights :

 1. Fix addressing of QT registers.
   WriteCoreReg needs byte address. So offsets need to be *4.
   IRI_QT_REG_ZZ_LPX_BITS_ADDR + (!s_lp)*4



Modified Files : HWEngine_61\show_iof_VDSL2.c

=========================================================================================
(04/4/08 Radha)
==========================================================================================

Highlights :

 1. New project vdsl_task_61.pj has been added to VDSL_Build_6.1.pj .

 2. preshow.c source file is added to VDSL_task_61.pj,
    as SFDQ initializations are different in BM5.0 and BM6.1 workspaces.

3. simtest_VDSL_6.1.dsp replaces simtest_VDSL.dsp in ModemHWBuild6.1 workspace as it refers to new preshow.c file.

4. LUT lookup tables are initialized, FDQ tables are initialized uing LUT concepts

Modified Files :

   \vdsl\vdsl_build_6.1.pj\simtest_VDSL_6.1.dsp         -(3)
   \vdsl\vdsl_build_6.1.pj\vdsl_task_61.pj              -(1)
   \vdsl\modem\source\vdsl_task_61\showtime\preshow.c   -(2)

   Modem\source\HWEngine_61\IRI_Ini.c  (4)
   Modem\source\HWEngine_61\IRI_IOF.c  (4)
   Modem\source\HWEngine_61\IRI_Iof_mfdq.c  (4)






=========================================================================================
(03/26/08 Radha Poluri)  -- after checkpoint
==========================================================================================

Highlights :

1. Modified/added code as RTV buffers are combined with Noise accumulator buffers and new SFDQ Exponent buffer is created in the QT BM.

2  Rx path registers are initialized for QT and QTP registers

3. LP3 parameters have been initialized.

Modified Files :

   Modem\source\HWEngine_61\IRI_Ini.c  (2,3)
   Modem\source\HWEngine_61\IRI_IOF.c  (2,3)
   Modem\source\HWEngine_61\TxDataPumpSetup.c (2,3)
   Modem\source\HWEngine_61\RxDataPumpSetup.c   (2,3)
   Modem\source\VDSL_Platform_61\LL_IOF.c   (1)


=========================================================================================
(03/25/08 Vivek Goel)  -- after checkpoint
==========================================================================================

Highlights :

Modified/added code for initialization of Tx/Rx registers that are used for pointerless
interleaving/ de-interleaving operation.

Modified Files :

   Modem\source\HWEngine_61\RxDataPumpSetup_VDSL1.c
   Modem\source\HWEngine_61\RxDataPumpSetup_VDSL2.c
   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL1.c
   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL2.c

=========================================================================================
=========================================================================================
(03/18/08 John Greszczuk)
==========================================================================================

Highlights :

 1. Initialize TxConstellation and Rx Constellation gain tables. (No longer regsiters with default value due to Pram )
 2. Fix assignment of Inactive Pointers to access port 0. ( the second arg of GetToneReorderingTableAddress() was
    changed to Port from Set.  ---Revisit this! to change the LLio function back as modem code should not need port)

 3. Program  QT_TX_ACTIVE registers.

 3. calculate and Program QTP registers with stats about BAT table - number 0 and greater than 1 bit tones.



Modified Files :

   Modem\source\HWEngine_61\IRI_Iof.c        [3]
   Modem\source\HWEngine_61IRI_Ini.c         [1,2]
   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL1.c   [4]

=========================================================================================
(03/16/08 Vivek Goel)
==========================================================================================

Highlights :
ZIT_CW_SIZE register is renamed as ZIT_I_SIZE in the ILV BM and the fields within the
register have been moved around. Made appropriate fixes to the TxDataPumpSetUp files to
match the BM changes.

Modified Files :

   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL1.c
   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL2.c

=========================================================================================
(03/14/08 John)
==========================================================================================

Highlights :
 Define  CO_VDSL_61 when building  HWEngineLib_6.1
 This is needed because the #ifdef is used in LL_IOf.h

Project: VDSL_build_6.1.pj
File: build\HWEngineLib_6.1\HWEngineLib_61.dsp



=========================================================================================
(03/12/08 Radha)
==========================================================================================

Highlights :

 1. New release notes file HWEngineLib6.1_release_notes.txt is added
   at   vdsl\modem\source\HWEngine_61\ to include all the changes in the firmware.

 2. Function return types are modified as the correponding prototypes
   have been modified in the header file by JB in previous 1079 Checkins.

 3. Merging of the changes JB made in computing
   ComputeTx/RxTransferSize() and CaptureTx/RxBitsInFifo() functions.

 4.  Function return value is modified in ConfigZephyrIlvTxIFM_VDSL2(),ConfigZephyrIlvTxIFM(),
   ConfigZephyrIlvRxDFM_VDSL2(),ConfigZephyrIlvRxDFM()  as zero return value is failing the ModemHWEngineBuild6.1

 5. HWexec6.1.dsp has been resynchonized with HWExec5.0.dsp as new files are added to the HWExec5.0.dsp workspace.



Modified Files :

   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL1.c - (2,4)
   Modem\source\HWEngine_61\TxDataPumpSetup_VDSL2.c - (2,4)
   Modem\source\HWEngine_61\RxDataPumpSetup_VDSL1.c - (2,4)
   Modem\source\HWEngine_61\RxDataPumpSetup_VDSL1.c - (2,4)
   Modem\source\HWEngine_61\show_iof_VDSL2.c        - (3)
   \vdsl\vdsl_build_6.1.pj\HWExec_61.dsp             -(5)









