1@Check DMAR table presence.
2@Verify checksum of DMAR structure.
3@Verify registers for each VT-d engine.
4@Verify DMAR structure length.
5@Verify reserved fields are 0s.
6@Verify remapping structures are valid.
7@Verify presence of at least one DRHD.
8@Verify IR flag in DMAR is consistent with CAP_reg.
9@Verify IR support is consistent across all VT-d engines.
10@Verify that IR capability in ECAP_reg is also in DMAR.
11@Verify DRHD for each PCI segment.
12@Verify each PCI segment reported in DMAR is valid.
13@Verify that PCI device is valid in Device Scope structure.
14@Verify the order in which VT-d engines are listed.
15@Verify each VT-d engine in HW has an associated DRHD.
16@Verify that each PCIe Root Port is listed in Device Scope.
17@Verify that IOAPIC is properly enumerated in Device Scope.
18@Verify the requester_id for IOxAPIC is valid in Device Scope.
19@Verify that HPET is properly enumerated and is MSI capable.
20@Verify the requester_id for HPET is valid in Device Scope.
21@Verify each IOxAPIC in MADT is listed in DRHD, when IR is supported.
22@Verify that MSI capable HPETs are listed in Device Scope, when IR is supported.
23@Verify presence of DRHD with INCLUDE_PCI_ALL flag set.
24@Verify the validity of device type in each Device Scope.
25@Verify the base & sub class codes, if IOxAPIC is enabled.
26@Verify IOxAPIC as a Root Complex Integrated device.
27@Verify that PCI endpoint is PCI enumerable and has header type 0.
28@Verify that all devices in DRHD are visible in PCI config space.
29@Verify the PCIe device as root port.
38@Verify at least one Device Scope in each RMRR.
39@Verify that only PCI endpoints listed in Device Scope of RMRR.
40@Verify 4k granularity of RMRR regions.
41@Verify that RMRR is only for USB controllers or iGfx.
42@Verify RMRR for USB, if platform supports USB emulation.
43@Verify that DRHD for catch all engine only includes IOxAPIC or HPET Device Scopes.
44@Verify that there is only one DRHD with INCLUDE_PCI_ALL.
45@Verify the order of different remapping structures.
46@Verify the validity of HPA and GPA for platform.
47@Verify each PCI device is enumerated under only one remapping engine.
48@Verify the validity of each PCI device listed in DMAR table.
49@Verify that MMIO BARs are unique and 4K aligned.
50@Verify initialization of the shadow GTT is done when VT-d is enabled.
51@Check VTx presence and enable matches SMBIOS Type 131 table.
52@Verify that Queued Invalidation capability in ECAP_reg is set when Interrupt Remapping is supported.
53@Verify that IOAPIC has no duplicate ID in Device Scope.
54@Verify that only 1 device scope for each HPET timer block.
55@Check VTx presence and properly enabled and locked on each core.
56@VT-d superpage should only be enabled when iGfx is disabled.
57@BIOS should not disable snoop control on default VT-d engine.
58@DMA Remapping engine configuration register should be locked after configuration.
59@There should be a corresponding device scope entries for each device listed in ANDD structures.
60@There should NOT exist any Type 5 device scope entries in DMAR if there is not any ANDD structure.
61@Each ACPI device number in ANDD structure must have a corresponding enumeration ID in Device Scope.
62@VTd Support for Large Pages (2MB and 1GB) on DEFAULT and GFX VTd Unit.
63@Graphics VTd Unit Support for SVM (Shared Virtual Memory).
64@SVM Page Fault Feature should not be enabled on Gfx VTd Unit.
65@Processor Graphics Support for PASID/ATS.
