2019 EC RELEASE NOTES

V01.16 12-02-2019
-----------------
- TGL Security[A2][BETA_BLOCKER] : After, EC Capsule Up-gradation/Down-gradation EC version not changing in bios page & ESRT Log 
- Added suppport for TGL UP3 GCS board with board ID: 0xF. 
- Added support for second fan tach read on Tach1 (GPIO051) - only for GCS board. Tach RPM populated on ACPI offset 0x75, 0x76. BIOS need to sync up. 
- HSD 1608196314: Added IMVP & charger settings for TGL GCS.
- Added support for GCS Keyboard
- HSD 1608947560: [TGL UP3 GCS] Need EC code change for fan PWM control
- RCR 1507630367: [TGL-U] EC to support CCG PD Firmware Update through IO port
- Ported PD Fw update patch from ICL to TGL. Below 3 RCRs are for the same cause combined.
- RCR 2209584499: PD FW Update Capsule & EFI Utility
- RCR 14010453097: EC Team must adapt from ICL Cypress PD 
- RCR 14010453098: EC team needs to commit to design and analyze the TI994 FW capsule upgrade protocol.
- HSD 2209871983: [TGL UP3 A6 19H2]]Cons]CPU Fan with connected PWM header is not rotating continuously with IFWI_WW46.5 [regr]
- HSD 2209254592: [TGL U A6] PWM Fan does not get trigger to Run/Start after a OS:BSODs, although temperature keep rising above limit.
- HSD-1407569079:[CCG-PD] Skip PD i2c interface reset during init as controller does this by default when powered on.

V01.15 11-18-2019
-----------------
- HSD 1607662987: [TGL _U] [A3/A2] : Fast charging is not happening  on TGL U Set up.
- HSD 1608231464: VCCST_PWRGD and PM_PCH_PWROK generation by EC in TGL UP3 and UP4 AEPs violating PDG
- HSD 1607513813: [TGL U AEP] SUT fails to wake from DS5 with PWRBTN in MAF mode config
- Re-enabled pwrbtn based on the ACPI offset set using the BtnSCICtl host command.
- Fixed klockwork issues on memset.

V01.14 11-02-2019
-----------------
- Fixed the boot issue on TGL Y fab2.
- Null pointer check on PD FW version check, in case PD FW APP mode fails. 
- HSD 1608241787: [TGL GC_ROC_DC1][UP4][CORP][CONS][Regression]:Hung with post code :109A after flashing 43.1IFWI
- Updated i2c addresses for boards as, Fab1: 0x20, 0x24, 0x23 & Fab2: 0x20, 0x24, 0x21.
- HSD 2209424072: [TGL U][UP3][Alpha UP4][PD] ProcHot - Need DCProcHot limit for 2S battery in EC FW - Need to validate Power Boss E2E with fProcHot

V01.13 09-26-2019
-----------------
- Adding support for both TIPD988 and TIPD994
- HSD 1607586077: [TGL-Y] [A2]: Type-C PD charging is not happening on TGL-Y setup.
- HSD 1507379292: [TGL Y] [A2] : PD Firmware version is not showing in BIOS Platform settings page

V01.12 09-03-2019
-----------------
- Interrupt based processing of SMC Host output. 
- HSD 2208126422: [TGL_A2_19H1][PM]:CAT error with PC:0005 observed system restarted with USB-C charger connected
- EC to not enque new OOB request until getting response for previous one. 
- HSD 1409537318: TGL PM:[Peci over eSPI]S5 cycling hang waiting for completetion for SB NP Message
- HSD 2206499883: [EC][CML][TGL]: Remove deprecated DPTF parameters from ACPI namespace

V01.11 08-06-2019
-----------------
- HSD 1606909496: [TGL][KSC] EC should raise Error post code on  S5/4 signal assert timeout after PM_RSMRST_
- HSD 1607490805: Scan matrix FW change needed for TGL U AEP G-tech keyboard
- Fixed the compilation issue of the previous check in.
- Fixing memset and memcpy klockwork issue

V01.10 07-17-2019
-----------------
- Added support for TGL Y AEP. 
- Added new platform config - Board Type - to isolate between RVP & AEP.
- Couple of GPIO changes to check Board type, rather thand board ID, cause now we have 2 skus in APE - U & Y.
- Changed the sensor table name from CNL to TGL_RVP.
- TypeC Config to return MaxSinkPwr & current values for TI PD on Y skus rather than static constants.
- Updated charger settings for TGL AEP U & Y.
- HSD 2207801605: [ICLU][EC] PMAX updates only every 2500mW change [Ported fix from ICL]
- HSD 1607220181: [EC-RCR]: TGL Y AEP Charger Settings
- HSD 2207494146: [EC-RCR]: TGL U AEP Charger Settings
- Ported below fixes from ICL CL # 637839, CL # 636358:
- B503 - Fatal Error solution. 
- HostRstAck to mirror HostRstWarn state
- SCI En/Disable control based on HostRstWarn & PltRst state.
- HSD 1409343267: TGL PO: PD  Firmware version Not showing in BIOS platform settings Page
- New EC algorithm for Fan control in Non ACPI mode.
- HSD 2207519894: [TGL A0 PO] EC Fan control based on CPU temperature does not work in IFWI 18.6 with EC 1.06 and thermally trimmed A0 parts
- HSD 2208017549: [TGL-Y]  PWM Fan control based on CPU temperature does not work in IFWI 29.1 with EC 1.09 and thermally trimmed parts
- HSD 1409687518: TGL U HeatSink issue reated to heat

V01.09 07-15-2019
----------------
- HSD 1607379959: [TGL A0 PO]: Fan is not rotating if the temperature crosses active trip point at OS hung condition(BSOD) 
- HSD 2207675948: [TGL] [A0 PO] Tgl U + 2S battery  - 10x slower charging than Tgl Y ERB  (same battery, same charger IC)
- HSD 2207782934: TGL-U RVP 2S and 3S Battery Support

V01.08 05-24-2019
-----------------
- Added support for additional boards: TGL Y LP4 CRB (0x7) & LP4 CRB SV (0x9)
- Type C Port config based on platform SKU type rather than board ID. U- CCG, Y - TI 
- PoE driver fix ported from ICL, where board randomly shutdown due to wrong temp data reading.
- HSD 1607167339 [TGL][EC]:EC Bios communication for current flash sharing mode.
- HSD 2207541039, 2207593643: [TGL] [A0 PO] Pmax tracking is not live data on 2S battery, DBPT 3.0.  Need for Pmax/Psys adaptive PD on TgL platforms(UY)
- Ported PMax framework from ICL with support for UVTH & DBPT v3.0 supported battery parameters.

V01.07 05-06-2019
-----------------
- HSD 1507091158 : [EC][ERB PO]TGL :  SUT is not getting charged with Dead Battery connected  upon connecting PD bricks.
- Added board id support for TGL U LP4, LP5 and TGL Y LP4
- Changed VP board ID from 0x31 to 0x21. 
- TGL AEP Support

Specific changes for AEP support: 
- Added 2nd table in bsp to switch from RVP to AEP based on BrdId. 2nd table just copied.
- IO Expander GPIOs updated. All board ID GPIOs on pins.
- Added Platform Config table for AEP. 
- Board type check based on RVP_AEP_ID (GPIO001). Then for AEP, 4 pins configured for BrdID reading. 
- Individual GPIO changes from RVP to AEP: 
	> GPIO007 : Unused - make input
	> GPIO010 : Unused
	> GPIO012 : Unused
	> GPIO021 : Unused
	> GPIO026 : PS2 -> GPIO input
	> GPIO035 : GPIO output
	> GPIO036 : Use as PwrBtn Output - most imp.
	> GPIO051 : Unused
	> GPIO052 : Unused -> moved to GPIO036
	> GPIO060 : Input -> PLN
	> GPIO103 : Unused
	> GPIO105 : Output OD -> VCCST_PWRGD new thing
	> GPIO114 : PS2 -> GPIO input
	> GPIO115 : PS2 -> GPIO input
	> GPIO121 : GPIO -> ADC input
	> GPIO123 : SPI -> Output (RSMRST) 
	> GPIO127 : PS2 -> GPIO input
	> GPIO135 : SPI -> GPIO input (RSMRST_PWRGD)
	> GPIO136 : SPI -> GPIO Output (PCH_DPWROK) [Should get driven by BootRom only, coming out of DSlp]
	> GPIO145 : Unused
	> GPIO146 : Unused
	> GPIO155 : GPIO -> ADC input
	> GPIO160 : Unused (was RSMRST_PWRGD on RVP)
	> GPIO165 : Unused
	> GPIO166 : Unused
- Updated bsp tables for PowerOn, PowerOff, Sus, and respective functions. 
- In bsp header file, made sure of all RVP pins those have different purpose on AEP (/if they not used in AEP),
  they check the board ID to assure they're on RVP.
- Configured AEP to support 4 type C CY PD ports - just like TGL U RVP.
- New thermal sensor table for AEP that has 6 sensors.
- ACPI table supports only upto 5 thermal sensors, added todo note for 6th sensor addition in the table. 
- VCCST_PWRGD driven high / low after ALL_SYS_PWRGD in powerOn / Off. 


v01.06 04-11-2019
----------------
- New Board ID codes added. 
- Timeouts En/Dis-abled based on PMC GPIO for CRB board.
- Board ID mask changed from 5 bits to 6 bits.  
- Disable EC debug prints 
- HSD 2207324176: [EC-RCR]: IMVP 9 programming register setting for Z0 and Z0 to A0 board conversion
- HSD 2206285896: [TGL_U_ERB PO] TGL Need EC programming of VRs on TGL ERB solution
- HSD 1409227696: TGL Z0:Incorrect IMVP9 settings causing the new platforms not to boot from G3.
- HSD 1409231414: [TGL Z0 PO] RVP does not boot after flashing IFWI WW13.5
- Added retries on IMVP read failures. 

V01.05 03-05-2019
----------------
- Implemented fix for proper EC Error LED Blinking based on post codes according to the release document.
- Changed the format specifier for minor version.
- HSD 1606840473: TGL Read and Write fan speed in EDK shell is not working.
- HSD 2206673592: Fan RPM speed is always at the max despite the active 2 policy is requesting different (lower) RPM speed
- HSD 1606909178: System is not booting when CC and CV values set from reading the battery

V01.04 02-06-2019
----------------
- HSD 2206509179: [TGL_U_ERB PO]   SUT should Boot to OS with Dead Battery with all supported PD bricks w/wo real battery attached
- HSD 1606840447: Active trip point & Critical trip point is not working  in EDK shell and OS level

V01.03 01-15-2019
----------------
- Added SysPwr_OK signal
- Updated IMVP changes; however they are still disable until further investigation.
- Enabled PECI_OVER_ESPI with a strap, Repurposed ESPI_TESTCRD_DET strap for PECI_OVER_ESPI_STRAP.
- POE strap (ESPI_TESTCRD_DET_STRAP_SW) is on SW6J2.4 on TGL U & Y. 
- Enabled OOB messages (GetTemp, RTC), and eSPI OOB Test interface.
- Ported eSPI handshake fixes from ICL, where OOBs were broken in MAF mode. Also, changed VW ready bit set in ISR. 
- Fixed Power Button Functionality
- HSD 1606875424: [EC][ERB PO]TGL : "UCM-UCSI ACPI Device " yellow bang is observed in device manager
- Fixing the compilation issue due to function declaration

V01.02 01-10-2019
----------------
- HSD 2206438484: Battery is not charging up on TGL ERB PO
- Battery Charger configuration TGL Y provided by PD team.
- Hard coding the cc and cv values(WA).  
  This will be reverted once that HSD 1606909178 is fixed

V01.01 12-14-2018
----------------
- HSD #2206438484: [ERB PO]   Battery is not charging up on TGL ERB PO
- Updated charger settings as per data provided by PD Team (Teal)

V01.00 11-21-2018
----------------
- This fix has the necessary changes required to bring up the TGL ERB board.
- Most of the GPIOs are mapped to the latest TGL-U Schematics
- The IMVP programming part is also implemented in the same fix.
- HSD 2206285896: TGL Need EC programming of VRs on TGL ERB solution

V0.15 09-19-2018
================
- Match the GPIO's to the TGL-U schematics. Align AppInit / PlatformConfig to ICL.
- HSD 1606678470: "Lid button" option is not available in OS with EC 0.15
- HSD 1606681542: "Platform Settings/ HID Event Filter" option is not available in BIOS with EC 0.15

V0.14 08-01-2018
- HSD 2204837266: [TGL][HFPGA] [EC] EC Card stuck in Power Plane init after the platform reset

V0.13 07-02-2018
- HSD 1305796714: In Powerplane, It was found that the kernel max execution time for when the TO are disabled wasn't being set properly, 
  the logic was reversed allowing only a short time for when the TO was disable. This was causing the kernel to timeout in the execution and try
  to recover the task. There is still a problem given that the task could not recover, but the execution time configuration was fixed.
- HSD 1407122121: For Deep Sx flow, the feature was disabled for VP since it was not implemented in the WB. Changed the configuration to enable it.
- For AC only flows. Because of complications implementing run-time battery removal in simics, it was agreed to use BATT_ID to disable the battery 
  to be able to test AC only flows. In BatInit, code was added to clear all battery ACPI registers and indicate that the battery is not present.
  This was done because the simulated smart battery could not be disconnected cleanly from the I2C bus and the battery remnoval code is based on
  the device not responding.
- Added configuration bit to disable thermal management. This after Euclid reported a problem of issuing a thermal shutdown due to random data 
  since there are no thermistors.

V0.12 06-28-2018
- Removed second funtion for power button management and put the up/down SCI functionality in the powerplane function
- All power button SCIs verified

V0.11 06-13-2018
- *Support for all TGL platforms with a single binary: VP and HFPGA*
- Removed the use of compilation flags for VP and Euclid. Functionality moved to PlatformConfig
- Functionality specific for Euclid is controlled with the EuclidWAEnable configuration bit
- If no IO Expander, EC return the default platform ID for PSS and assumes it is a HFPGA
- Removed references to ICL and board IDs to replace them with TGL
- Removed unused GPIO definitions
- Added a flag to the Makefile so that if the binary is an engineering release the debug output will display:
  "*** THIS IS AN ENGINEERING RELEASE ***" after the EC version
- Improved battery manager debug messages
- Removed WA that was preventing EC to identify low battery during Power On flow. Now EC won't boot if battery is low

V0.10 06-04-2018
- Enable power button function in periph.c to send power buton up and down SCIs
- Fix for the platform ID reported for Euclid card.

V0.9 05-16-2018
- Enabled Home and Volume buttons
- Debug messages to validate temperature sensors 
- EC returns the value for platform id (bom, board and fab ids) from the Simics variables.
- Fixed order of the platform ID. The bytes were swaped

V0.8 04-24-2018
- * Release for IFWI *
- Most all features are implemented but need full integration to test
- Removed WA for ICL affecting the platform/board ID
- Removed unnecessary code for LPC

V0.7 04-04-2018
- Added debug outputs
- Enable serial port delay this looks to be to let the clock stabilize. Without this, the first debug messages are garbled.
- Added and error for when the board ID can't be read
- Added text file with VP commands

V0.6 03-15-2018
---------------
- First instance to be checked in to Perforce
- Based on ICL_PD branch with special development emphasis in VP and HFPHA


NOTES:
=====
Required Hardware:
    Euclid Board
    Dediprog to program KSC binary image.

Flash Programming:
    1) Power off the Euclid board completely and disconnect all the power sources.
    2) Change jumper to put board in Force dediprog state
    3) Connect the Dediprog SF600 to EC Programming header
    4) Open the Dediprog software and select the chip "W25Q128FV"
    5) Select the 16MB integrated image (output of FIT tool)
    6) Power the Euclid board
    7) Click on Batch to perform erase/program/verify (Make sure the programming starts from offset 0)
    8) After programming disconnect dediprog and Power off the Euclid board.
    9) Change jumper back to normal mode and power the board.

VP Commands:
===========
Please check the WB release notes Wiki:
https://securewiki.ith.intel.com/display/PPA/TGL+EC+WB+-+Model+Release+Notes 


* To set temperature in thermistors 1-4:
  -------------------------------------

> set-thermistor-temp tgl.mb.ec.dev_thermistor<X> <TEMP>

Where X is the absolute thermistor number: X=3 -> thermistor 1, X=4 -> thermistor 2, X=5 -> thermistor 3, X=6 -> thermistor 4
And TEMP is the temperature in deg C

Example, set thermistor1 to 25 C:

> set-thermistor-temp tgl.mb.ec.dev_thermistor3 25 

* Power button:
  ------------

power-button-press

* Scan-matrix key pressed:
  -----------------------
tgl.mb.ec.ksc.kbd_matrix.key-press-wake-up Ksi_bit = 0-7 

* Simulated Battery/power commands:
  ----------------------
@attach_ac() - Attaches the AC barrel to the system
@detach_ac() - Detaches the AC barrel and enables battery mode
@set_battery_level(<percent>) - Sets the battery to the desired percentage (integer)
@update_charger(current)      - Sets the charging current in mA

* Buttons:
  -------
tgl.mb.ec.home-button
tgl.mb.ec.home-volume-up
tgl.mb.ec.home-volume-down

* Virtual Battery Enablement
----------------------------
Note: Please run these before starting Simics
@virtual_battery_switch_open() - Normal battery operation
@virtual_battery_switch_close() - Enables virtual battery
