Document Number: 620548-1.0

Tiger Island

Schematics PDF – FAB A

March 2020

Intel Confidential

Important Notice:

1.

The content of this document is still under development and the product has

yet to be verified. The information provided here is subject to

change/modification in the next release.

2.

The final version of the document will be available after the product has been

validated.

tiger-html.html

Tiger Island

March 2020

Schematics PDF

Intel Confidential

Document Number: 620548-1.0

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products

described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject

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.

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Copyright © 2020, Intel Corporation. All rights reserved.

tiger-html.html

March 2020

Tiger Island

Document Number: 620548-1.0

Intel Confidential

Schematics PDF

Revision History

Date

Revision

Description

March 2020

0.5

Initial release.

§

tiger-html.html

PBA : K56089-100

PB : K56090-100

REV: 1.00

TIGER ISLAND

TA : K56088-100

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INTEL CONFIDENTIAL
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LB5G2

LB5G1

LB7G1

LB4K1

EMPTY

WEEE_LABEL_9X5MM

SERIAL_NUMBER

SILKSCREEN

LABEL

MAC_ADDRESS

LABEL

MAC_ADDRESS

COVER PAGE

INTEL CORPORATION

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LEGAL STATEMENT

SVID JUMPERS

INTEL CORPORATION

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1

CHANGELOG

PWR : SEQUENCE II/GLITCH FREE

PWR : SEQUENCE I

PWR : VCCST/VCCSTG

PWR : LAN RAIL

PWR : V12_S/V5_S/V3P3_S/V1P8_S

PWR : VCCIN PH2

PWR : VCCIN PH1

PWR : VCCIN

PWR : VNN/V1P05_A BYPASS

PWR : VCCIN_AUX

PWR : VDDQ_VPP

PWR : VDDQ_MEM/VDDQ_VTT

PWR : V1P8_A

PWR : V5_A/V3P3_A

PWR : V12_IN/RTC/BTN

B2B CONN : 80 PIN IO B2B

MISC : HDR/LEDS/FAN

SIO : RS485 HEADER

SIO : RS232 HEADER

SIO : F81804U

HDA : AUDIO JACK

HDA : ALC662_VD

SATA & ESATA : SATA PORT/PWR HDR

USB 3.1 : STACKED STD CONN X2

USB 3.1 : CMC & ESD 2

USB 3.1 : CMC & ESD 1

RJ45 : RJ45 STACKED CONN

PHY : 88E2110 PWR

PHY : 88E2110

GBE : I225 FOXVILLE

M.2 KEY B : NANO SIM SLOT

M.2 KEY B : SLOT

M.2 KEY E : CLINK, RF_KILL

M.2 KEY E : SLOT

LVDS : PWR & HDR

LVDS : DDI SIGNALS

DP++ : STD CONN

DP++ : CMC/ESD

HDMI : HDMI CMC/ESD & CONN

HDMI : HDMI ALS

SPI : TPM 2.0

SPI : FLASH & HDR

SPI : FLASH FET SWITCH

SODIMM CH1 : PWR DECAP

SODIMM CH1 : CONN 2

SODIMM CH1 : CONN2

SODIMM CH0 : PWR DECAP

SODIMM CH0 : CONN 1

SODIMM CH0 : CONN 1

STRAP : PCH STRAPS 3

STRAP : PCH STRAPS 2

STRAP : PCH STRAPS 1

STRAP : CPU STRAPS 2

STRAP : CPU STRAPS 1

DECAP : VDD2

DECAP : VCCIN_AUX/CCST/VCCSTG

DECAP: VCCIN

CPU : JTAG/MISC

CPU : XDP/FIVR DEBUG

CPU : GND

CPU : PCH POWER

CPU : CPU POWER

CPU : VCCIN

CPU : SYS PWR MANAGEMENT

CPU : PCIE CLOCK

CPU : CNV/CSI

CPU : PCIE/USB/SATA

CPU : AUDIO HDA/I2S

CPU : I2C/UART/SPI

CPU : SPI/SMB/SML/ESPI

CPU : MEMORY CH1

CPU : MEMORY CH0

CPU : DISPLAY

POWER SEQUENCE DIAGRAM

POWER MAP

BLOCK DIAGRAM

TABLE OF CONTENTS

LEGAL STATEMENT

COVER PAGE

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TABLE OF CONTENTS

SHEET NAME

SHEET NUMBER

SHEET NAME

TABLE OF CONTENTS

SHEET NUMBER

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BLOCK DIAGRAM

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TABLE - LED, KEY JUMPERS, SWITCHES, EC ERROR CODE

POWER MAP

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TABLE - LED, KEY JUMPERS, SWITCHES, EC ERROR CODE

POWER SEQUENCE DIAGRAM

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NC

NC

NC

STD DP

SPACING 380UM

TC_RCOMP MAIN ROUTE TRACE

STD HDMI 1

B2B

LVDS

DDIA_RCOMP MAIN ROUTE TRACE
SPACING 380UM

CPU : DISPLAY

SET PIN DK45 AS GPIO

CR-7 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE7

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1

TP4P3

1

TP4P2

2

1

R4P4

2

1

R6C2

2

1

R6C3

DM8

AN2
AN1

BK1

BJ2

BK2

BJ1
BM7

BH5

BM5

BH7
BK5
BK7

BF1

BE2

BF2

BE1
BD7

AY5

BD5

AY7
BB5
BB7

AT2

AU1

AT1

AU2
AD5

AH7

AD7

AH5
AF7
AF5

AY2

BB1

AY1

BB2
AM5

AT7

AM7

AT5
AP7
AP5

DK27

DM29

DT6

DN4

DD6

DF6

DV8

DU8

DR5

DN21

DK23

DM23

DN23

DJ47

DG47

DF47

DF45

DG43

DF43

DK45

DH52

M8

CE4

T12

Y11

T9

V11

T11

Y9

P9

V9

AB9

AD9

AC2

AD2

AF1

AG2

AC1

AD1

AF2

AG1

AB1

AJ2
AJ1

DN8

DG10

U5E1

45B8

64B3

29B2

29B5

64A8

40B6
43A6

64A8

30B5

43C8

43C5

30B8

40B6

40B6

44C8
44C8

64C3

64C3

64A8

64A8

64C3

64C3

64C3

64C3

40B6

42A8
42A8

64C3

43C8

64C3

40B6

42B8

43C5

42D8

42D8

42B8

42C8

42C8

40B6

40B6

40B6

40B6

40B6

40B6

44B8

44B8

44C8

44D8

44D8

BMAP_REV=1.2

TGL_U_IP

SOC

LPID6529

1 OF 21

150
1%
CH
0402LF
1/16W

1%

CH

0402LF

150

CH

5%

100K

0402LF

TP

TP

DDIA_BKLTCTL

DDSP_HPD3

GPPC_D12_DDP4_SDA

GPPC_D10_DDP3_SDA

DDSP_HPD1
DDSP_HPD2

GPPC_D9_DPP3_SCL

GPPC_E21_DDP2_SDA

GPPC_E20_DDP2_SCL

GPPC_E19_DDP1_SDA

GPPC_E18_DDP1_SCL

DDIA_TX1_DP
DDIA_TX1_DN

DDIA_RCOMP

TC_RCOMPN

TC_RCOMPP

TCP2_TX1_DN

TCP2_TXRX1_DN

DSI_DE_TE_2

TCP2_AUX_DN

TCP2_AUX_DP

TCP2_TX0_DN

TCP2_TX0_DP

TCP2_TX1_DP

TCP2_TXRX1_DP

DDI1_HDMI_DATA2_DN
DDI1_AUX_DP
DDI1_AUX_DN

DDI2_DP_LANE3_DP
DDI2_DP_LANE3_DN

TCP2_TXRX0_DN

DDI2_DP_AUX_DN

TCP2_TXRX0_DP

DDI1_HDMI_DATA2_DP

DDI2_DP_LANE2_DN

DDI2_DP_AUX_DP

DDI2_DP_LANE0_DN

DDI2_DP_LANE0_DP

DDI2_DP_LANE2_DP

DDI2_DP_LANE1_DN

DDI2_DP_LANE1_DP

DDI1_HDMI_DATA0_DN

DDI1_HDMI_DATA0_DP

DDI1_HDMI_DATA1_DN

DDI1_HDMI_DATA1_DP

DDI1_HDMI_CLK_DN

DDI1_HDMI_CLK_DP

DDPA_HPD

DDIA_AUX_DN

DDIA_AUX_DP

DDIA_TX0_DN

DDIA_TX0_DP

CPU : DISPLAY

DESIGN NOTE:

INTEL CORPORATION

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CAD NOTE:

CAD NOTE:

DESIGN NOTE:

BI

BI

IN

IN

DISP_UTILS

DDIA_RCOMP

DSI_DE_TE_2

TCRCOMPN

TCRCOMPP

TCP3_AUXPAD_N

TCP3_AUXPAD_P

TCP3_TX_N0

TCP3_TX_P0

TCP3_TX_N1

TCP3_TX_P1

TCP3_TXRX_N0

TCP3_TXRX_P0

TCP3_TXRX_N1

TCP3_TXRX_P1

TCP2_AUXPAD_N

TCP2_AUXPAD_P

TCP2_TX_N0

TCP2_TX_P0

TCP2_TX_N1

TCP2_TX_P1

TCP2_TXRX_N0

TCP2_TXRX_P0

TCP2_TXRX_N1

TCP2_TXRX_P1

TCP1_AUXPAD_N

TCP1_AUXPAD_P

TCP1_TX_N0

TCP1_TX_P0

TCP1_TX_N1

TCP1_TX_P1

TCP1_TXRX_N0

TCP1_TXRX_P0

TCP1_TXRX_N1

TCP1_TXRX_P1

TCP0_AUXPAD_N

TCP0_AUXPAD_P

TCP0_TX_N0

TCP0_TX_P0

TCP0_TX_N1

TCP0_TX_P1

TCP0_TXRX_N0

TCP0_TXRX_P0

TCP0_TXRX_N1

TCP0_TXRX_P1

BKLTCTL

BKLTEN

VDDEN

GPPC_A_15_USB2_OCB_2_DDSP_HPD_4_I2S4_SCLK_DISP_MISC_4

GPPC_A_14_USB2_OCB_1_DDSP_HPD_3_I2S3_RXD_DISP_MISC_3_DMIC_CLK_B_1

GPPC_A_20_DDSP_HPD_2_DISP_MISC_2_I2S5_SFRM

GPPC_A_19_DDSP_HPD_1_DISP_MISC_1_I2S5_SCLK

GPPC_A_17_DISP_MISC_C_I2S4_TXD

GPPC_D_12_ISH_SPI_MOSI_DDP4_CTRLDATA_CAS_SPIM_MOSI_TBT_LSX3_B_GSPI2_MOSI_CAS_SPIS_MOSI

GPPC_D_11_ISH_SPI_MISO_DDP4_CTRLCLK_CAS_SPIM_MISO_TBT_LSX3_A_GSPI2_MISO_CAS_SPIS_MISO

GPPC_D_10_ISH_SPI_CLK_DDP3_CTRLDATA_CAS_SPIM_CLK_TBT_LSX2_B_GSPI2_CLK_CAS_SPIS_CLK

GPPC_D_9_ISH_SPI_CSB_DDP3_CTRLCLK_CAS_SPIM_CS0B_TBT_LSX2_A_GSPI2_CS0B_CAS_SPIS_CSB

GPPC_E_21_DDP2_CTRLDATA_TBT_LSX1_B

GPPC_E_20_DDP2_CTRLCLK_TBT_LSX1_A

GPPC_E_19_DDP1_CTRLDATA_TBT_LSX0_B

GPPC_E_18_DDP1_CTRLCLK_TBT_LSX0_A

GPPC_A_22_DDPC_CTRLDATA_I2S5_RXD

GPPC_A_21_DDPC_CTRLCLK_I2S5_TXD

GPPC_A_18_DDSP_HPD_B_DISP_MISC_B_I2S4_RXD

GPPC_H_17_DDPB_CTRLDATA

GPPC_H_16_DDPB_CTRLCLK_PCIE_LNK_DOWN

DDIB_AUXN

DDIB_AUXP

DDIB_TXN_0

DDIB_TXP_0

DDIB_TXN_1

DDIB_TXP_1

DDIB_TXN_2

DDIB_TXP_2

DDIB_TXN_3

DDIB_TXP_3

GPPC_E_14_DDSP_HPD_A_DISP_MISC_A

GPPC_E_23_DDPA_CTRLDATA

GPPC_E_22_DDPA_CTRLCLK_DNX_FORCE_RELOAD

DDIA_AUXN

DDIA_AUXP

DDIA_TXN_0

DDIA_TXP_0

DDIA_TXN_1

DDIA_TXP_1

DDIA_TXN_2

DDIA_TXP_2

DDIA_TXN_3

DDIA_TXP_3

BI

BI

BI
BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

T_POINT1
T_POINT1

OUT

OUT

OUT
OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

BI

OUT

BI

IN

BI
BI

BI
BI

IN

BI

tiger-html.html

CPU : MEMORY CH0

NC

NC

TP

DDR_COMP MAIN ROUTE TRACE SPACING 500UM

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2

1

R6T12

2

1

R6T10

2

1

R7F1

DV47

BB44

BK44

CK44

CT44

BA51

BG51

CK51

CR51

BD44

BH44

CM44

CV44

BA50

BG50

CK50

CR50

BD47

BB47

BD45

BB45
BB42
BB41

BD42
BD41

BK47
BK45

BH47
BH45
BH42

BK42
BK41

BH41

CK47

CM47

CK45

CM45

CK42

CM42
CM41

CK41

CT47

CV47

CT45

CV45

CT42

CV42

CT41

CV41

AY53
AY52
AY50
AY49

BC53
BC52
BC50
BC49

BF53
BF52
BF50
BF49

BH53
BH52
BH50
BH49

CH53
CH52
CH50
CH49

CL53
CL52
CL50
CL49

CP53
CP52
CP50
CP49

CU53
CU52
CU50
CU49

E52

BT47

BT45

BP47
BP42
BP45
BP44

BL53

BP52
BP53

BN53

BN51

CD42
CD41

CD47

CD45

CA53

CA51

CE50

CE53

C49

BV45

CF44
CF45

CB47
CB44
CB45
CF41
BU53
BT51
BV42
BU50
BY53
CA50
BY52
BY50
CD51
CD53
BV47
CE52
BV41

CF42
CF47

BT42

CC52

BT41

CC53

BU52
BL50

BN50
BL52

CB42
BV44

BT53

AU49

AU50

U5E1

31C7

31B4

31A5 34A5 31B7
34B7

31A4

31B4

31B4

31C4

31D4

31B4

31C4

31B1
31B1
31B1
31B1

31C1

31C7
31C7

31C7
31C7

31C7

31C7
31C7

31B1
31B1
31B1
31B1
31C1

31C1
31C1
31B1
31C1
31C1

31C7

31C7

31C7

31C7

31C1

31C7

31C7

31B7

31B7

31B7

32C5

68A5

31D4

31C4

31C4

31D8

VDDQ_MEM

SOC

TGL_U_IP

BMAP_REV=1.2

2 OF 21

LPID6529

100
1%
CH
0402LF
1/16W

0402LF CH

5%

0

1/16W

0402LF

5%

470

CH

M_0_BG0

M_0_DQ_6<7..0>

DRAM_RESET_N_R

M_0_DQ_7<7..0>

M_0_DQ_5<7..0>

6

M_0_DQ_3<7..0>

6

M_0_DQ_4<7..0>

6

M0_3CA4
M0_3CA3
M0_3CA2

M_0_DQS_7_DP
M_0_DQS_7_DN
M_0_DQS_6_DP
M_0_DQS_6_DN

M_0_DQS_2_DP

M_0_CLK_DDR1_DP
M_0_CLK_DDR1_DN

M0_2CLK_DP
M0_2CLK_DN
M0_1CLK_DP
M0_1CLK_DN

M_0_CLK_DDR0_DP
M_0_CLK_DDR0_DN

M0_3CKE0

M0_2CKE0
M0_2CKE1
M0_1CKE0
M0_1CKE1
M0_0CKE0

M_0_CKE_0

M_0_CS1_N
M_0_CS0_N

M0_0CA0
M0_0CA1
M0_2CS0
M0_3CA5

M_0_DQS_5_DP
M_0_DQS_5_DN
M_0_DQS_4_DP
M_0_DQS_4_DN
M_0_DQS_3_DP

M_0_DQS_2_DN
M_0_DQS_1_DP
M_0_DQS_1_DN
M_0_DQS_0_DP
M_0_DQS_0_DN

M_0_ODT0

M_0_BG1

M_0_BA1

DDR_COMP_0

M_0_CKE_1

M0_0CKE1

M0_3CKE1

M_0_DQS_3_DN

M_0_ODT1

M_0_BA0

M_0_ACT_N

M_0_PARITY

M_0_ALERT_N
V_DDR0_VREF_CA

DDR_VTT_CTRL

DRAM_RESET_N

M_0_DQ_2<7..0>

M_0_DQ_1<7..0>

M_0_DQ_0<7..0>

M_0_MA<16..0>

CPU : MEMORY CH0

0

1

2

3

4

5

6

8
7

9

12
11
10

13

14

15

16

7
6
5
4
3
2
1
0

7
6
5
4
3
2
1
0

0

1

2

3

4

5

7

0

1

2

3

4

5

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

3
2
1
0

5
4

6

7

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

BI

OUT

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

OUT

OUT

IN

BI

OUT

OUT

OUT

BI
BI
BI

DDR_COMP

DRAM_RESETB

DDR_VTT_CTL

DDR0_VREF_CA

DDR0_ALERT_N

DDR_0PAR_3CS1_3CS0_3CA3

DDR_0ACTN_2CS1_2CS0_2CA3

DDR_0BA0_3CA0_3CA0_3CA6

DDR_0BA1_1CA5_1CA6_1CA0

DDR_0BG0_2CA3_2CA4_2CS1

DDR_0BG1_2CA2_2CA3_2CS0

DDR_0MA0_NC_3CS1_3CA4

DDR_0MA1_NC_0CS1_0CA4

DDR_0MA2_3CS0_3CA2_3CA2

DDR_0MA3_0CS1_0CS0_0CA3

DDR_0MA4_0CS0_0CA2_0CA2

DDR_0MA5_0CA5_0CA6_0CA0

DDR_0MA6_0CA3_0CA4_0CS1

DDR_0MA7_0CA4_0CA5_0CA1

DDR_0MA8_0CA2_0CA3_0CS0

DDR_0MA9_2CA0_2CA0_2CA6

DDR_0MA10_3CA1_3CA1_3CA5

DDR_0MA11_NC_2CS1_2CA4

DDR_0MA12_2CA1_2CA1_2CA5

DDR_0MA13_1CS1_1CS0_1CA3

DDR_0MA14_1CA2_1CA3_1CS0

DDR_0MA15_1CA3_1CA4_1CS1

DDR_0MA16_1CA4_1CA5_1CA1

DDR_0ODT0_1CS0_1CA2_1CA2

DDR_0ODT1_1CA0_1CA0_1CA6

DDRDQSN_IL00_NIL00_LP00

DDRDQSP_IL00_NIL00_LP00

DDRDQSN_IL01_NIL01_LP01

DDRDQSP_IL01_NIL01_LP01

DDRDQSN_IL10_NIL02_LP10

DDRDQSP_IL10_NIL02_LP10

DDRDQSN_IL11_NIL03_LP11

DDRDQSP_IL11_NIL03_LP11

DDRDQSN_IL02_NIL04_LP20

DDRDQSP_IL02_NIL04_LP20

DDRDQSN_IL03_NIL05_LP21

DDRDQSP_IL03_NIL05_LP21

DDRDQSN_IL12_NIL06_LP30

DDRDQSP_IL12_NIL06_LP30

DDRDQSN_IL13_NIL07_LP31

DDRDQSP_IL13_NIL07_LP31

DDR_NC_3CA2_3CA3_3CS0

DDR_NC_3CA3_3CA4_3CS1

DDR_NC_3CA4_3CA5_3CA1

DDR_NC_3CA5_3CA6_3CA0

DDR_NC_2CS0_2CA2_2CA2

DDR_NC_0CA1_0CA1_0CA5

DDR_NC_0CA0_0CA0_0CA6

DDR_0CS0_NC_1CS1_1CA4

DDR_0CS1_1CA1_1CA1_1CA5

DDR_0CKE0_2CA5_2CA6_2CA0

DDR_0CKE1_2CA4_2CA5_2CA1

DDR_NC_0CKE1_0WCKN_0WCKN

DDR_NC_0CKE0_0WCKP_0WCKP

DDR_NC_1CKE1_1WCKN_1WCKN

DDR_NC_1CKE0_1WCKP_1WCKP

DDR_NC_2CKE1_2WCKN_2WCKN

DDR_NC_2CKE0_2WCKP_2WCKP

DDR_NC_3CKE1_3WCKN_3WCKN

DDR_NC_3CKE0_3WCKP_3WCKP

DDR_0CLKN0_0CLKN_0CLKN_0CLKN

DDR_0CLKP0_0CLKP_0CLKP_0CLKP

DDR_NC_1CLKN_1CLKN_1CLKN

DDR_NC_1CLKP_1CLKP_1CLKP

DDR_NC_2CLKN_2CLKN_2CLKN

DDR_NC_2CLKP_2CLKP_2CLKP

DDR_0CLKN1_3CLKN_3CLKN_3CLKN

DDR_0CLKP1_3CLKP_3CLKP_3CLKP

DDRDQ_IL13_NIL07_LP31_0

DDRDQ_IL13_NIL07_LP31_1

DDRDQ_IL13_NIL07_LP31_2

DDRDQ_IL13_NIL07_LP31_3

DDRDQ_IL13_NIL07_LP31_4

DDRDQ_IL13_NIL07_LP31_5

DDRDQ_IL13_NIL07_LP31_6

DDRDQ_IL13_NIL07_LP31_7

DDRDQ_IL12_NIL06_LP30_0

DDRDQ_IL12_NIL06_LP30_1

DDRDQ_IL12_NIL06_LP30_2

DDRDQ_IL12_NIL06_LP30_3

DDRDQ_IL12_NIL06_LP30_4

DDRDQ_IL12_NIL06_LP30_5

DDRDQ_IL12_NIL06_LP30_6

DDRDQ_IL12_NIL06_LP30_7

DDRDQ_IL03_NIL05_LP21_0

DDRDQ_IL03_NIL05_LP21_1

DDRDQ_IL03_NIL05_LP21_2

DDRDQ_IL03_NIL05_LP21_3

DDRDQ_IL03_NIL05_LP21_4

DDRDQ_IL03_NIL05_LP21_5

DDRDQ_IL03_NIL05_LP21_6

DDRDQ_IL03_NIL05_LP21_7

DDRDQ_IL02_NIL04_LP20_0

DDRDQ_IL02_NIL04_LP20_1

DDRDQ_IL02_NIL04_LP20_2

DDRDQ_IL02_NIL04_LP20_3

DDRDQ_IL02_NIL04_LP20_4

DDRDQ_IL02_NIL04_LP20_5

DDRDQ_IL02_NIL04_LP20_6

DDRDQ_IL02_NIL04_LP20_7

DDRDQ_IL11_NIL03_LP11_0

DDRDQ_IL11_NIL03_LP11_1

DDRDQ_IL11_NIL03_LP11_2

DDRDQ_IL11_NIL03_LP11_3

DDRDQ_IL11_NIL03_LP11_4

DDRDQ_IL11_NIL03_LP11_5

DDRDQ_IL11_NIL03_LP11_6

DDRDQ_IL11_NIL03_LP11_7

DDRDQ_IL10_NIL02_LP10_0

DDRDQ_IL10_NIL02_LP10_1

DDRDQ_IL10_NIL02_LP10_2

DDRDQ_IL10_NIL02_LP10_3

DDRDQ_IL10_NIL02_LP10_4

DDRDQ_IL10_NIL02_LP10_5

DDRDQ_IL10_NIL02_LP10_6

DDRDQ_IL10_NIL02_LP10_7

DDRDQ_IL01_NIL01_LP01_0

DDRDQ_IL01_NIL01_LP01_1

DDRDQ_IL01_NIL01_LP01_2

DDRDQ_IL01_NIL01_LP01_3

DDRDQ_IL01_NIL01_LP01_4

DDRDQ_IL01_NIL01_LP01_5

DDRDQ_IL01_NIL01_LP01_6

DDRDQ_IL01_NIL01_LP01_7

DDRDQ_IL00_NIL00_LP00_0

DDRDQ_IL00_NIL00_LP00_1

DDRDQ_IL00_NIL00_LP00_2

DDRDQ_IL00_NIL00_LP00_3

DDRDQ_IL00_NIL00_LP00_4

DDRDQ_IL00_NIL00_LP00_5

DDRDQ_IL00_NIL00_LP00_6

DDRDQ_IL00_NIL00_LP00_7

BI

BI

OUT

OUT

OUT

OUT

OUT

BI
BI

BI

BI

BI

BI

tiger-html.html

CPU : MEMORY CH1

CR-9 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE9

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 9 OF 80

INTEL CONFIDENTIAL
<>

K36

G44

AJ44

AV44

D39

C45

AG51

AN51

K38

J44

AL44

AR44

C39

D45

AG50

AN50

G38
G36

H36
H38
N36

L36
L38

N38

G42
G41

J41
J42

G45

J45

G47

J47

AJ41
AJ42

AL41
AL42

AJ45
AJ47

AL45
AL47

AR41

AV42

AR42

AV41

AR45

AV45

AR47

AV47

E38

D38

B38
A38
E41

D40

B40
A40

A43
B43

D43

E44
A46
B46

D46

E47

AF53
AF52
AF50
AF49

AH53
AH52
AH50
AH49

AL53
AL52
AL50
AL49

AP53
AP52
AP50
AP49

R45

R47

N42
N45
N44
N47
J53

M52
M53

K53

K51

AC42
AC41

AC45

AC47

W53

W51

AC50
AC53

U45

AE44
AE45

AA47
AA44
AA45
AE41
P53
N51
U42
P50
U53
W50
U52
U50
AA51
AA53
U47
AC52
U41

AE42
AE47

R41

Y52

R42

Y53

P52
J50

K50
J52

AA42
U44

N53

AU52

AU53

U5E1

34B4

34A4

34B4

34C4

34D4

34B4

34B4

34C4

34C1
34C1

34C7

34C7
34C7

34C7

34C7

34C7

34B1

34B1

34B1

34B1
34B1
34B1
34B1
34B1

34B1

34C1

34C1

34C1

34C1

34B1

34C7

34C7
34C7

34B7

34B7

34B7

34C7

34C7
34C7

34C7

35C5

34C7

34C4

34C4

34D4

34D8

3 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

M_1_DQ_4<7..0>

M_1_DQ_5<7..0>

6

M_1_DQ_3<7..0>

6

6

M_1_DQ_7<7..0>

M_1_DQ_6<7..0>

M1_0CA1

M1_2CS0

M1_3CA2

M1_0CKE1

M1_0CKE0

M1_1CKE1

M1_1CKE0

M1_2CKE1

M1_3CKE1

M1_3CKE0

M1_1CLK_DN

M1_1CLK_DP

M1_2CLK_DN

M1_2CLK_DP

M1_3CA3

M1_2CKE0

M1_0CA0

M1_3CA4

M1_3CA5

M_1_DQS_0_DP
M_1_DQS_0_DN

M_1_ODT1

M_1_CLK_DDR0_DP
M_1_CLK_DDR0_DN

M_1_CLK_DDR1_DN

M_1_CLK_DDR1_DP

M_1_CKE_1

M_1_DQS_6_DP

M_1_DQS_7_DN

M_1_DQS_7_DP

M_1_DQS_6_DN
M_1_DQS_5_DP
M_1_DQS_5_DN
M_1_DQS_4_DP
M_1_DQS_4_DN

M_1_DQS_1_DP

M_1_DQS_2_DP

M_1_DQS_3_DN

M_1_DQS_3_DP

M_1_DQS_2_DN

M_1_DQS_1_DN

M_1_CKE_0

M_1_CS1_N
M_1_CS0_N

M_1_PARITY

M_1_ALERT_N

M_1_ACT_N

M_1_BG1

M_1_BA1
M_1_BA0

M_1_BG0

V_DDR1_VREF_CA

M_1_ODT0

M_1_DQ_0<7..0>

M_1_DQ_1<7..0>

M_1_DQ_2<7..0>

M_1_MA<16..0>

CPU : MEMORY CH1

4
3
2
1
0

7
6
5
4
3

0

1

2

7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7

5
4
3
2
1
0
7

5
4
3
2
1
0
7

5
4
3
2
1
0
7

5

6

2

3

4

0

1

5

6

7

16
15
14
13
12
11

8

9

10

7
6
5
4
3
2
1
0

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

OUT

OUT
OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

DDR1_VREF_CA

DDR1_ALERT_N

DDR_1PAR_7CS1_7CS0_7CA3

DDR_1ACTN_6CS1_6CS0_6CA3

DDR_1BA0_7CA0_7CA0_7CA6

DDR_1BA1_5CA5_5CA6_5CA0

DDR_1BG0_6CA3_6CA4_6CS1

DDR_1BG1_6CA2_6CA3_6CS0

DDR_1MA0_NC_7CS1_7CA4

DDR_1MA1_NC_4CS1_4CA4

DDR_1MA2_7CS0_7CA2_7CA2

DDR_1MA3_4CS1_4CS0_4CA3

DDR_1MA4_4CS0_4CA2_4CA2

DDR_1MA5_4CA5_4CA6_4CA0

DDR_1MA6_4CA3_4CA4_4CS1

DDR_1MA7_4CA4_4CA5_4CA1

DDR_1MA8_4CA2_4CA3_4CS0

DDR_1MA9_6CA0_6CA0_6CA6

DDR_1MA10_7CA1_7CA1_7CA5

DDR_1MA11_NC_6CS1_6CA4

DDR_1MA12_6CA1_6CA1_6CA5

DDR_1MA13_5CS1_5CS0_5CA3

DDR_1MA14_5CA2_5CA3_5CS0

DDR_1MA15_5CA3_5CA4_5CS1

DDR_1MA16_5CA4_5CA5_5CA1

DDR_1ODT0_5CS0_5CA2_5CA2

DDR_1ODT1_5CA0_5CA0_5CA6

DDRDQSN_IL04_NIL10_LP40

DDRDQSP_IL04_NIL10_LP40

DDRDQSN_IL05_NIL11_LP41

DDRDQSP_IL05_NIL11_LP41

DDRDQSN_IL14_NIL12_LP50

DDRDQSP_IL14_NIL12_LP50

DDRDQSN_IL15_NIL13_LP51

DDRDQSP_IL15_NIL13_LP51

DDRDQSN_IL06_NIL14_LP60

DDRDQSP_IL06_NIL14_LP60

DDRDQSN_IL07_NIL15_LP61

DDRDQSP_IL07_NIL15_LP61

DDRDQSN_IL16_NIL16_LP70

DDRDQSP_IL16_NIL16_LP70

DDRDQSN_IL17_NIL17_LP71

DDRDQSP_IL17_NIL17_LP71

DDR_NC_4CA0_4CA0_4CA6

DDR_NC_4CA1_4CA1_4CA5

DDR_NC_6CS0_6CA2_6CA2

DDR_NC_7CA2_7CA3_7CS0

DDR_NC_7CA3_7CA4_7CS1

DDR_NC_7CA4_7CA5_7CA1

DDR_NC_7CA5_7CA6_7CA0

DDR_1CS0_NC_5CS1_5CA4

DDR_1CS1_5CA1_5CA1_5CA5

DDR_1CKE0_6CA5_6CA6_6CA0

DDR_1CKE1_6CA4_6CA5_6CA1

DDR_NC_4CKE1_4WCKN_4WCKN

DDR_NC_4CKE0_4WCKP_4WCKP

DDR_NC_5CKE1_5WCKN_5WCKN

DDR_NC_5CKE0_5WCKP_5WCKP

DDR_NC_6CKE1_6WCKN_6WCKN

DDR_NC_6CKE0_6WCKP_6WCKP

DDR_NC_7CKE1_7WCKN_7WCKN

DDR_NC_7CKE0_7WCKP_7WCKP

DDR_1CLKN0_4CLKN_4CLKN_4CLKN

DDR_1CLKP0_4CLKP_4CLKP_4CLKP

DDR_NC_5CLKN_5CLKN_5CLKN

DDR_NC_5CLKP_5CLKP_5CLKP

DDR_NC_6CLKN_6CLKN_6CLKN

DDR_NC_6CLKP_6CLKP_6CLKP

DDR_1CLKN1_7CLKN_7CLKN_7CLKN

DDR_1CLKP1_7CLKP_7CLKP_7CLKP

DDRDQ_IL17_NIL17_LP71_0

DDRDQ_IL17_NIL17_LP71_1

DDRDQ_IL17_NIL17_LP71_2

DDRDQ_IL17_NIL17_LP71_3

DDRDQ_IL17_NIL17_LP71_4

DDRDQ_IL17_NIL17_LP71_5

DDRDQ_IL17_NIL17_LP71_6

DDRDQ_IL17_NIL17_LP71_7

DDRDQ_IL16_NIL16_LP70_0

DDRDQ_IL16_NIL16_LP70_1

DDRDQ_IL16_NIL16_LP70_2

DDRDQ_IL16_NIL16_LP70_3

DDRDQ_IL16_NIL16_LP70_4

DDRDQ_IL16_NIL16_LP70_5

DDRDQ_IL16_NIL16_LP70_6

DDRDQ_IL16_NIL16_LP70_7

DDRDQ_IL07_NIL15_LP61_0

DDRDQ_IL07_NIL15_LP61_1

DDRDQ_IL07_NIL15_LP61_2

DDRDQ_IL07_NIL15_LP61_3

DDRDQ_IL07_NIL15_LP61_4

DDRDQ_IL07_NIL15_LP61_5

DDRDQ_IL07_NIL15_LP61_6

DDRDQ_IL07_NIL15_LP61_7

DDRDQ_IL06_NIL14_LP60_0

DDRDQ_IL06_NIL14_LP60_1

DDRDQ_IL06_NIL14_LP60_2

DDRDQ_IL06_NIL14_LP60_3

DDRDQ_IL06_NIL14_LP60_4

DDRDQ_IL06_NIL14_LP60_5

DDRDQ_IL06_NIL14_LP60_6

DDRDQ_IL06_NIL14_LP60_7

DDRDQ_IL15_NIL13_LP51_0

DDRDQ_IL15_NIL13_LP51_1

DDRDQ_IL15_NIL13_LP51_2

DDRDQ_IL15_NIL13_LP51_3

DDRDQ_IL15_NIL13_LP51_4

DDRDQ_IL15_NIL13_LP51_5

DDRDQ_IL15_NIL13_LP51_6

DDRDQ_IL15_NIL13_LP51_7

DDRDQ_IL14_NIL12_LP50_0

DDRDQ_IL14_NIL12_LP50_1

DDRDQ_IL14_NIL12_LP50_2

DDRDQ_IL14_NIL12_LP50_3

DDRDQ_IL14_NIL12_LP50_4

DDRDQ_IL14_NIL12_LP50_5

DDRDQ_IL14_NIL12_LP50_6

DDRDQ_IL14_NIL12_LP50_7

DDRDQ_IL05_NIL11_LP41_0

DDRDQ_IL05_NIL11_LP41_1

DDRDQ_IL05_NIL11_LP41_2

DDRDQ_IL05_NIL11_LP41_3

DDRDQ_IL05_NIL11_LP41_4

DDRDQ_IL05_NIL11_LP41_5

DDRDQ_IL05_NIL11_LP41_6

DDRDQ_IL05_NIL11_LP41_7

DDRDQ_IL04_NIL10_LP40_0

DDRDQ_IL04_NIL10_LP40_1

DDRDQ_IL04_NIL10_LP40_2

DDRDQ_IL04_NIL10_LP40_3

DDRDQ_IL04_NIL10_LP40_4

DDRDQ_IL04_NIL10_LP40_5

DDRDQ_IL04_NIL10_LP40_6

DDRDQ_IL04_NIL10_LP40_7

BI

BI

BI

BI

BI

BI

tiger-html.html

10K OHM : 100 KHZ

499 OHM : 1 MHZ (DEFAULT)

PLACE RA CLOSE TO

RA

RA

PCH WITHIN 15MM

PLACE RA CLOSE TO

PCH WITHIN 15MM

RA

RA

CPU : SPI/SMB/SML/ESPI

PCH WITHIN 15MM

PLACE RA CLOSE TO

RA

RA

PLACE RA CLOSE TO

PCH

RA

2.2K OHM : 400 MHZ

CR-10 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE10

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 10 OF 80

INTEL CONFIDENTIAL
<>

DV24

DW47
DW49

A48

U5E1

2

1

R2J2

2

1

R4G8

2

1

R4G1

2

1

R4F6

2

1

R6U2

2

1

R4F7

2

1

R4G10

1

TP6R8

2

1

R6P7

2

1

R6P8

2

1

R6P18

2

1

R6P17

2

1

R7P2

2

1

R6P9

DF39

DJ35

DJ33

DG35

DJ39

DF35

DG37

DJ37

DF2

DH4

DH3

DN10

DV14

DK15

DK13

DM13

DN13

DJ15

DN15

DW9

DK6

DM6

DJ6

DK8

DV11

DT8

DN5
DR9

DJ17

DK17

DN17

DM17

DK19

DN19

DM19

DK21

CY50

DL50

DN53

DK52

DJ53
DH50
DP50
DP52

U5E1

60C2 60C7

10C2

60A6 60C2 60C7

10C2

60C2 60C7

10C2

60C2 60B7

10C2

10C2

60B2 60C7

10C2

60B2 60C7

10C2

60B2 60C7

47C8

47C8

47C8

51D8

51B7

51D8

29C4

28C5

39B2

10C2 50D7

10C2

10C2

10B4

37C8
28B2

37A8

28C2

37A8

37C8

10A5 32A2 40C6 64B8 44A5 57A7
10A5 32A2 40C6 44A5 57A7 64B8

10A7 50D7
10A7 50D7
30A5

10A7

10D2 50D7

28B5

37C8

37A8
37A8

29C3

65A4

28A8 64B8

10A4

10A4

30C8

10A7

10A4

10A4
10A4
10B4

10D2 32A2 40C6 44A5 57A7 64B8
10D2 32A2 40C6 64B8 44A5 57A7

V3P3_A

V3P3_A

V3P3_S

BMAP_REV=1.2

LPID6529

SOC

TGL_U_IP

5 OF 21

1%

499

0402LF
1/16W

CH

499
1%

1/16W

0402LF

CH

0402LF

CH

5%

1/16W

1K

0402LF
1/16W

1K

CH

5%

499

0402LF

1%
CH

1/16W

499

1/16W

0402LF

CH

1%

TP

1%

15

0402LF CH

1%

15

0402LF CH

1%

15

0402LF CH

1%

15

0402LF CH

1%

50

0402LF CH

0

0

0402LF CH

0

0

0402LF CH

LPID6529

SOC

BMAP_REV=1.2

TGL_U_IP

4 OF 21

SIO_ESPI_CS_N

GPPC_A4_ESPI_CS_N

SIO_ESPI_RST_N

GPPC_A6_ESPI_RST_N

SIO_ESPI_IO0

GPPC_A0_ESPI_IO_0

SIO_ESPI_CLK

GPPC_A5_ESPI_CLK

GPPC_A3_ESPI_IO_3

SIO_ESPI_IO1

GPPC_A1_ESPI_IO_1

SIO_ESPI_IO2

GPPC_A2_ESPI_IO_2

SIO_ESPI_IO3

CNV_WLAN_CLINK_RST_N

CNV_WLAN_CLINK_DATA

CNV_WLAN_CLINK_CLK

GPPC_F17_SGMII_MDC

GPPC_F18_SGMII_MDIO

GPPC_E10_SPI1_CS0_N

GPPC_E6_SPI1_RST_N

GPPC_E13_TPM_IRQ

SML0_DATA

SML1_CLK

SML1_DATA

GPPC_A6_ESPI_RST_N

SPI0_CLK
SPI0_IO_3
SPI0_IO_2
SPI0_MISO

SMB_SCL
SMB_SDA

SML0_CLK
SML0_DATA
GPPC_C5_SML0ALERT_N

SML1_CLK

SML0_CLK

CPU : SPI/SMB/SML/ESPI

SPI0_MOSI
SPI0_CS1_N
SPI0_CS0_N
SPI0_TPM_CS_N

GPPC_E11_SPI1_CLK_N

GPPC_E8_SATA_LED_N

GPPC_C2_SMBALERT_N

GPPC_A2_ESPI_IO_2

GPPC_A5_ESPI_CLK

GPPC_B23_SML1ALERT_N

SML1_DATA

GPPC_A3_ESPI_IO_3

GPPC_A1_ESPI_IO_1
GPPC_A0_ESPI_IO_0
GPPC_A4_ESPI_CS_N

SMB_SDA
SMB_SCL

CAD NOTE:

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

GPPC_A_6_ESPI_RESETB

GPPC_A_4_ESPI_CSB

GPPC_A_0_ESPI_IO_0

GPPC_A_1_ESPI_IO_1

GPPC_A_2_ESPI_IO_2_SUSWARNB_SUSPWRDNACK

GPPC_A_3_ESPI_IO_3_SUSACKB

GPPC_A_5_ESPI_CLK

GPPC_B_23_SML1ALERTB_PCHHOTB_GSPI1_CS1B

GPPC_C_7_SML1DATA

GPPC_C_6_SML1CLK

GPPC_C_5_SML0ALERTB

GPPC_C_4_SML0DATA

GPPC_C_3_SML0CLK

GPPC_C_2_SMBALERTB

GPPC_C_1_SMBDATA

GPPC_C_0_SMBCLK

MLK_RSTB

MLK_DATA

MLK_CLK

GPPC_F_17_GMII_MDC_THC1_SPI2_RSTB

GPPC_F_18_GMII_MDIO_THC1_SPI2_INTB

GPPC_F_16_GSXCLK_THC1_SPI2_CSB

GPPC_F_12_GSXDOUT_THC1_SPI2_IO_0

GPPC_F_13_GSXSLOAD_THC1_SPI2_IO_1

GPPC_F_14_GSXDIN_THC1_SPI2_IO_2

GPPC_F_15_GSXSRESETB_THC1_SPI2_IO_3

GPPC_F_11_THC1_SPI2_CLK

GPPC_E_6_THC0_SPI1_RSTB

GPPC_E_17_THC0_SPI1_INTB

GPPC_E_8_SPI1_CS1B_SATA_LEDB

GPPC_E_10_SPI1_CSB_THC0_SPI1_CSB

GPPC_E_13_SPI1_MOSI_IO_0_THC0_SPI1_IO_0

GPPC_E_12_SPI1_MISO_IO_1_THC0_SPI1_IO_1

GPPC_E_1_SPI1_IO_2_THC0_SPI1_IO_2

GPPC_E_2_SPI1_IO_3_THC0_SPI1_IO_3

GPPC_E_11_SPI1_CLK_THC0_SPI1_CLK

SPI0_TPM_CSB

SPI0_FLASH_0_CSB

SPI0_FLASH_1_CSB

SPI0_MOSI_IO_0

SPI0_MISO_IO_1

SPI0_IO_2

SPI0_IO_3

SPI0_CLK

OUT

OUT

BI

SPARE0

SPARE1

SPARE2

SPARE3

OUT

IN

OUT

IN

BI

BI

BI

BI

OUT

BI

BI

BI

BI

IN

BI
BI
BI
BI

BI

BI

BI

OUT

IN

T_POINT1

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

OUT

BI

BI

BI

BI

BI

OUT

OUT

BI
BI

tiger-html.html

TO IMVP

CPU :I2C/UART/SPI

PLACE RA CLOSE TO PCH,WITHIN 25.4MM

RA

B2B

GPPC_RCOMP MAIN ROUTE TRACE SPACING 100UM

UART HDR

B2B

B2B

B2B

UART HDR

TO LVDS

CR-11 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE11

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 11 OF 80

INTEL CONFIDENTIAL
<>

1

TP6R4

1

TP6R2

2

1

R4G9

2

1

R4G7

2

1

R4F3

DG17
DG19

DN33
DT35

DR51

DF25
DF27

DF29

DG29

DJ29
DJ31

DJ8
DR7
DR24
DU25

DV25
DT25

DR27
DW27

DV31
DU31
DT27
DV27

DJ19

DF21

DJ21

DG23

DJ23

DT18

DV18

DW18

DR18
DU19

DV19

DT19

DR21

DW21

DV21

DT21

CY53
CY52

CY49

DA50

DA51

DC49

DC53

DC52

DC50

DD47
DD44

CY39
DB47

DB45
DB44

U5E1

48D1
48B8

50C8

76B7

72D4
72D4

63B3

63A2

63A2

63B3

44B6

60C7

64B8

64B8

28B7

48A4

28C7

64B8

64C3

64C3
64C3

64C3

63B1

63A4

63A4

63B1

63A1

63A4

63A1

63A4

63A2

63A3

63A3

63A2

64A2

64B3

64A2

64B3

64A4

64B3

64A4

64B3

47A5

47A5

47A4

46A8

48D1

48C1

64B8

TGL_U_IP

BMAP_REV=1.2

SOC

LPID6529

6 OF 21

1%

200

CH

1/16W

0402LF

1%

CH

15

0201LF

GPPC_D1_KEYB_FCP_OFF

GPPC_RCOMP

GPPC_D0_KEYB_RST

GPPC_E16_LAN_WAKE_N

GPPC_B8_V3P3_LAN_EN

GPPC_B10_I2C5_SCL
GPPC_B9_I2C5_SDA

UART2_TXD
UART2_RXD

GPPC_D18_LVDS_IRQ

GPPC_E15_ESPI_ALERT

GPPC_T2_DEBUG

GPPC_T3_DEBUG

GPPC_B22_SPI1_MOSI_R

CPU : I2C/UART/SPI

GPPC_B20_SPI1_CLK_R

GPPC_B18_SPI0_MOSI
GPPC_B17_SPI0_MISO
GPPC_B14_SPI0_CS1

GPPC_B20_SPI1_CLK
GPPC_B22_SPI1_MOSI
GPPC_B21_SPI1_MISO

UART0_TXD
UART0_RXD
UART0_CTS
UART0_RTS

UART1_TXD
UART1_RXD
UART1_CTS
UART1_RTS

UART2_CTS
UART2_RTS

I2C2_SCL
I2C2_SDA

I2C3_SCL
I2C3_SDA

CNV_MFUART2_TXD
CNV_MFUART2_RXD

GPPC_D14_KEYE_RST

GPPC_D13_KEYE_WAKE

GPPC_D15_KEYB_DISABLE_N

GPPC_D16_KEYB_WAKE_N

GPPC_B19_SPI1_CS0

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT

IN

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

BI

BI

BI

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

GPPC_U_4_GSPI3_CS0B

GPPC_U_5_GSPI3_CLK

GPPC_T_2_I2C7_SDA_FUSA_DIAGTEST_EN

GPPC_T_3_I2C7_SCL_FUSA_DIAGTEST_MODE

GPPC_RCOMP

GPPC_D_0_ISH_GP_0_BK_0_CAS_GP_0_SBK_0

GPPC_D_1_ISH_GP_1_BK_1_CAS_GP_1_SBK_1

GPPC_D_2_ISH_GP_2_BK_2_CAS_GP_2_SBK_2

GPPC_D_3_ISH_GP_3_BK_3_CAS_GP_3_SBK_3

GPPC_D_17_ISH_GP_4_CAS_GP_4

GPPC_D_18_ISH_GP_5_CAS_GP_5

GPPC_E_15_ISH_GP_6

GPPC_E_16_ISH_GP_7

GPPC_B_9_I2C5_SDA_ISH_I2C2_SDA_CAS_I2C2_SDA

GPPC_B_10_I2C5_SCL_ISH_I2C2_SCL_CAS_I2C2_SCL

GPPC_B_7_ISH_I2C1_SDA_CAS_I2C1_SDA

GPPC_B_8_ISH_I2C1_SCL_CAS_I2C1_SCL

GPPC_B_5_ISH_I2C0_SDA_CAS_I2C0_SDA

GPPC_B_6_ISH_I2C0_SCL_CAS_I2C0_SCL

GPPC_D_15_ISH_UART0_RTSB_GSPI2_CS1B_IMGCLKOUT_5

GPPC_D_16_ISH_UART0_CTSB_SML0BALERTB_CAS_SPIM_CS1B

GPPC_D_13_ISH_UART0_RXD_SML0BDATA_I2C4B_SDA

GPPC_D_14_ISH_UART0_TXD_SML0BCLK_I2C4B_SCL

GPPC_H_8_I2C4_SDA_CNV_MFUART2_RXD

GPPC_H_9_I2C4_SCL_CNV_MFUART2_TXD

GPPC_H_6_I2C3_SDA

GPPC_H_7_I2C3_SCL

GPPC_H_4_I2C2_SDA

GPPC_H_5_I2C2_SCL

GPPC_C_18_I2C1_SDA

GPPC_C_19_I2C1_SCL

GPPC_C_16_I2C0_SDA

GPPC_C_17_I2C0_SCL

GPPC_C_22_UART2_RTSB_CNV_MFUART0_RTS_B

GPPC_C_23_UART2_CTSB_CNV_MFUART0_CTS_B

GPPC_C_20_UART2_RXD_CNV_MFUART0_RXD

GPPC_C_21_UART2_TXD_CNV_MFUART0_TXD

GPPC_C_14_UART1_RTSB_ISH_UART1_RTSB

GPPC_C_15_UART1_CTSB_ISH_UART1_CTSB

GPPC_C_12_UART1_RXD_ISH_UART1_RXD

GPPC_C_13_UART1_TXD_ISH_UART1_TXD

GPPC_C_10_UART0_RTSB

GPPC_C_11_UART0_CTSB

GPPC_C_8_UART0_RXD

GPPC_C_9_UART0_TXD

GPPC_B_19_GSPI1_CS0B

GPPC_B_21_GSPI1_MISO_NFC_CLKREQ

GPPC_B_22_GSPI1_MOSI

GPPC_B_20_GSPI1_CLK_NFC_CLK

GPPC_B_15_GSPI0_CS0B

GPPC_B_14_SPKR_TIME_SYNC_1_GSPI0_CS1B

GPPC_B_17_GSPI0_MISO

GPPC_B_18_GSPI0_MOSI

GPPC_B_16_GSPI0_CLK

BI

IN

OUT

OUT

IN

IN

OUT

BI

OUT

BI

IN

OUT

tiger-html.html

M.2 KEYB

SLAVE MODE : 13 OHMS

MASTER MODE : 33 OHMS

ALL SGMII* SIGNALS ARE ON 1.8V DOMAIN

I2S1 SERIES RES

RA
1.8V : 0 OHMS

PLACE RA RES CLOSE TO MCP

RA

TO STRAPPING

3.3V : 33 OHMS

I2S MODE

SNDW_RCOMP MAIN ROUTE TRACE SPACING 380UM

I2S TO M.2 KEYE

PLACE 75K OHM RESISTORS CLOSE TO MCP

PLACE 33 OHM RESISTORS CLOSE TO MCP

CPU : AUDIO HDA

I2S TO

PCIE4_RCOMP/N MAIN ROUTE TRACE SPACING 380UM

BT_KILL

WIFI_KILL

PLACE 33 OHM RESISTORS CLOSE TO MCP

I2S2 SERIES RES

CR-12 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE12

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 12 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4G5

2

1

R6R4

2

1

R8R6

2

1

C6R5

2

1

C6R1

2

1

R6R2

11

1

12

6

7

8

9

10

5

4

3

2

U7R1

2

1

R7R19

2

1

R3E21

2

1

R3E19

2

1

R3E20

2

1

R4P11

2

1

R3E11

2

1

R3E4

2

1

R3E15

2

1

R3E14

2

1

R6R5

DF33

DW15
DW24

DG41

DH49

DL52

DG50

DL49

DG51

DL53

DM31

DN31

DK31

DK33

DV35

DW35

DR35

DT32

DT38

DV38

DW38

DV41

DV37

DT37

DU37

DR38

U5E1

P5

T5

V5

Y5

P7

T7

V7

Y7

N1

R1

T1

V1

N2

R2

T2

V2

Y12
V12

U5E1

2

1

R4G6

2

1

R4G3

2

1

R4G2

2

1

R4G4

51B4 12C8

12C8

12C8

52A8

51B1

12B1

12B1

12B1
12B1

51B4

12D8

51B1
51B4

12D1

58A6
12A8

58B7

47C4

12A8

12A8

12A8

58B3

12C1

12D1

46D2

12D1

46C2

46C2

46D2

12C8

48C2

12D8

47B4

64B8
64B8

48C2

64B8

64B8

12B8
12B8

12B8

48C2

12D8

58B6
58B6

12B8

12D8

48C2

30C5

V1P8_A

V3P3_A

V1P8_A

0402LF CH

33 5%

0402LF CH

33 5%

5%

CH

0402LF

33

0402LF

33 5%

CH

LPID6529

8 OF 21

TGL_U_IP

BMAP_REV=1.2

SOC

SOC

7 OF 21

TGL_U_IP

BMAP_REV=1.2

LPID6529

0402LF

1%
CH

200

1/16W

0402LF

5%

33

CH

RESN

1%

0402LF

2.2K

33

0402LF

5%

CH

0402LF CH

33 5%

CH

5%

33

0402LF

CH

0402LF

33 5%

IC

0402LF

10K 5%

CH

6.3V

X5R

0.1UF

10%

0201LF

0.1UF

10%

X5R

0201LF

6.3V

CH

1%

0402LF
1/16W

75K

0201LF

EMPTY

1/20W

100K
5%

CH

0402LF

1%

75K

GPP_S1_SGMII_INT

GPP_S0_SGMII_AUXTS

GPP_S2_SGMII_RST_N

SGMII_RST_N
SGMII_PPS

GPP_S3_SGMII_PPS

GPP_S2_SGMII_RST_N

GPP_S0_SGMII_AUXTS
GPP_S1_SGMII_INT

GPPC_R6_I2S1_TXD

SGMII_AUXTS
SGMII_INT

GPPC_A8_I2S2_RST_N

GPP_R4_HDA_RST_N_R

GPP_R4_HDA_RST_N

GPPC_A7_I2S2_SCLK

GPP_R0_HDA_BCLK_R

GPPC_A13_KEYE_BTKILL

GPPC_A9_I2S2_TXD

GPPC_A10_I2S2_RXD

GPPC_A8_I2S2_RST_N

GPP_R3_HDA_SDI

GPPC_A9_I2S2_TXD

GPPC_A10_I2S2_RXD

KEYE_BT_PCMFRM_CRF_RST_N

GPPC_A7_I2S2_SCLK

KEYE_BT_PCMIN

KEYE_BT_PCMOUT_CLKREQ

KEYE_BT_PCMCLK

GPP_S3_SGMII_PPS

PCIE4_COM0_RCOMP_N

PCIE4_COM0_RCOMP_P

KEYB_I2S1_SFRM

GPPC_A23_I2S1_SCLK

GPPC_A11

PCIE4_0_TX_DP
PCIE4_0_TX_DN

GPP_R0_HDA_BCLK

KEYB_I2S1_TXD

LVL_OE

PCIE4_0_RX_DN

PCIE4_0_RX_DP

GPPC_A23_I2S1_SCLK
GPPC_R7_I2S1_SFRM

GPPC_R5_I2S1_RXD

KEYB_I2S1_RXD

GPPC_R5_I2S1_RXD

GPP_R1_HDA_SYNC_R

GPP_R2_HDA_SDO_R

GPPC_R6_I2S1_TXD

GPPC_R7_I2S1_SFRM

KEYB_I2S1_SCLK

SNDW_RCOMP

GPP_R1_HDA_SYNC

GPP_R2_HDA_SDO

CPU : AUDIO HDA/I2S

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

DESIGN NOTE:

CAD NOTE:

DESIGN NOTE:

DESIGN NOTE:

OUT

OUT

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

TXB0104RUTR

A4

VCCB

B1

B2

B3

B4

OE

GND

A3

A2

A1

VCCA

OUT
OUT

IN

OUT

IN

IN

OUT

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

IN
IN

OUT

IN

PCIE4_COM0_RCOMP_N

PCIE4_COM0_RCOMP_P

PCIE4_RX_N_0

PCIE4_RX_P_0

PCIE4_TX_N_0

PCIE4_TX_P_0

PCIE4_RX_P_1

PCIE4_RX_N_1

PCIE4_TX_N_1

PCIE4_TX_P_1

PCIE4_RX_N_2

PCIE4_RX_P_2

PCIE4_TX_N_2

PCIE4_TX_P_2

PCIE4_RX_N_3

PCIE4_RX_P_3

PCIE4_TX_N_3

PCIE4_TX_P_3

SNDW_RCOMP

GPPC_A_13_PMC_I2C_SCL_I2S3_TXD_DMIC_CLK_B_0

GPPC_A_11_PMC_I2C_SDA_I2S3_SCLK

GPPC_A_9_I2S2_TXD_MODEM_CLKREQ_CRF_XTAL_CLKREQ_DMIC_CLK_A_1

GPPC_A_10_I2S2_RXD_DMIC_DATA_1

GPPC_A_8_I2S2_SFRM_CNV_RF_RESET_B_DMIC_DATA_0

GPPC_A_7_I2S2_SCLK_DMIC_CLK_A_0

GPP_R_4_HDA_RSTB

GPP_R_3_HDA_SDI_0_I2S0_RXD_HDACPU_SDI

GPP_R_2_HDA_SDO_I2S0_TXD_HDACPU_SDO

GPP_R_1_HDA_SYNC_I2S0_SFRM

GPP_R_0_HDA_BCLK_I2S0_SCLK_HDACPU_BCLK

GPP_S_1_SNDW0_DATA_RGMII_INT

GPP_S_0_SNDW0_CLK_RGMII_AUXTS

GPP_S_3_SNDW1_DATA_DMIC_CLK_B_1_RGMII_PPS

GPP_S_2_SNDW1_CLK_DMIC_CLK_B_0_RGMII_RESET

GPP_S_5_SNDW2_DATA_DMIC_DATA_1

GPP_S_4_SNDW2_CLK_DMIC_CLK_A_1

GPP_S_7_SNDW3_DATA_DMIC_DATA_0

GPP_S_6_SNDW3_CLK_DMIC_CLK_A_0

GPP_R_5_HDA_SDI_1_I2S1_RXD

GPP_R_6_I2S1_TXD

GPP_R_7_I2S1_SFRM

GPPC_A_23_I2S1_SCLK

GPPC_D_19_I2S_MCLK1_OUT

GPPC_F_8_I2S_MCLK2_INOUT

tiger-html.html

2. ADVICE TO DEPOPULATE RA IF USING WWAN M.2 CARD

1. SATAGP1 HAVE INTERNAL PU.

RA

USB2_1

PCIE_RCOMP/N MAIN ROUTE TRACE SPACING 200UM

CPU : PCIE / USB / SATA

GEN 2

GEN 2

USB3_3

USB2_2

USB2_3

USB2.0 MAIN ROUTE TRACE SPACING 200UM

ESATA/B2B

SATA 0

M.2 KEYB

PHY

B2B

B2B

KEY B

USB3_1

USB3_2

M.2 KEY B

KEY E

B2B

TRIPAD

USB2_4

M.2 KEY E

GBE

USB3_4

CR-13 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE13

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 13 OF 80

INTEL CONFIDENTIAL
<>

2

1

R7T1

2

1

R1J1

2

1

R1H4

2

1

R1J3

2

1

R1J5

2

1

R1H5

2

1

R1J4

2

1

R1J2

2

1

R1J6

2

1

R6P11

2

1

R4C5

2

1

R4C2

2

1

R4D1

CV4

DD5

CW9

DD1

DA1

DA12

DC8

DB4

DA5

DC11

CY3

DD4

DA9

DD2

DA2

DA11

DC7

DB3

DA4

DC9

DC12
DF1
DE1

E3

BT7
BT8

CE2
CE1

BT9

BV9
CF4
CF3

BV7
BV8

CG2
CG1

BY7
BY8

CG5
CG4

CB8
CB7
CK5
CK4

CD9
CD8

CK1
CK2

CG8
CG7

CL4
CL3

CJ8
CJ7

CN2
CN1

CR8
CR7
CN5
CN4

CU8
CU7

CT2
CT1

CW8
CW7

CU3

CT4

DA8
DA7
CV2
CV1

DV9
DT9

DN29
DK29
DT31
DR32

DD8

DN6
DG8

DP4

DJ45

DF41

U5E1

48D8

64B3

64C8

48C8

56A4

55A4

56A4

55A4

50C8

50D8

46B8

48C8

55B4

46B7

46B7

46B8

50D8

50D8

51D4

48A6 48B6

64B3

13C7

13C7

57A2

13C7

64C8

57A2

64C8

57A2

64C8

57A2

48C6

48C6

54B8

56C1

54A4

13C7

57C6

55C8

54C4

57C6

57C6

64C8

64B8

48C8

55B4

55B8

54B4

54B4

54B8

56D1

54A4

56D4

54A4

57C6

56C4

54A4

64C8

56A1

55A4

55B8

56A1

55A4

51D8

55C8

48C8

46D8

46D8

64B3
64B3

55C4
55C4

48C8

48C6

48C6

13A8

13A8

13A8

13A8

51D8

51D4

64C8

54C4

54C8

54C8

56A5

29C8 56D5

LPID6529

BMAP_REV=1.2

TGL_U_IP

9 OF 21

SOC

CH

100 1%

0402LF

113
1%

1/16W

CH
0402LF

CH

1%

10K

1/16W

0402LF

1/16W

0402LF

1%
CH

10K

CH

0 5%

0402LF

5%

0402LF CH

0

PCIE_RCOMP_P
PCIE_RCOMP_N

USB2_ID

USB2_P6_DP

USB2_P8_DP

PCIE3_P9_RX_DP

PCIE3_P12_TX_DP

USB3_P3_RX_DN

USB3_P3_RX_DP

PCIE3_P7_RX_DN

PCIE3_P7_RX_DP

PCIE3_P6_TX_DP

PCIE3_P5_TX_DP

USB3_P4_TX_DN

PCIE3_P6_RX_DN

PCIE3_P6_RX_DP

PCIE3_P6_TX_DN

PCIE3_P7_TX_DN

PCIE3_P7_TX_DP

SGMII_0B_RXN

KEYB_WWAN_CONFIG1

USB2_P8_DN

PCIE3_P9_ESATA_TX_DN

PCIE3_P9_ESATA_RX_DP

ESATA_TX_DN

PCIE3_P9_ESATA_RX_DN

PCIE3_P9_TX_DP

ESATA_TX_DP

PCIE3_P9_TX_DN

ESATA_RX_DP

PCIE3_P9_RX_DN

ESATA_RX_DN

PCIE3_P5_RX_DP
PCIE3_P5_RX_DN

USB3_P1_TX_DP

USB3_P2_RX_DN

PCIE3_P9_ESATA_TX_DP

SATA0_RX_DN

USB2_P3_DN

USB2_P2_DP

SATA0_TX_DN
SATA0_RX_DP

PCIE3_P10_TX_DN

PCIE3_P10_RX_DN

PCIE3_P5_TX_DN

USB3_P4_TX_DP

USB3_P3_TX_DN

USB3_P2_TX_DN

USB3_P2_TX_DP

USB3_P1_TX_DN

USB3_P2_RX_DP

USB3_P1_RX_DP

SATA0_TX_DP

USB3_P1_RX_DN

PCIE3_P10_TX_DP

CPU : PCIE/USB/SATA

USB3_P4_RX_DN

USB3_P3_TX_DP

USB3_P4_RX_DP

SGMII_0B_TXP

USB2_P3_DP

USB2_P6_DN

USB2_P10_DN

USB2_P10_DP

USB2_P7_DP
USB2_P7_DN

USB2_P4_DP
USB2_P4_DN

PCIE3_P12_TX_DN
PCIE3_P12_RX_DP
PCIE3_P12_RX_DN

PCIE3_P9_ESATA_TX_DN
PCIE3_P9_ESATA_RX_DP
PCIE3_P9_ESATA_RX_DN

PCIE3_P9_ESATA_TX_DP

SGMII_0B_TXN
SGMII_0B_RXP

PCIE3_P10_RX_DP

USB2_P2_DN

USB2_P1_DN

USB2_P1_DP

SATA_PCIE_SELECTION

GPPC_A16_USB2_OC3_N

USB2_RCOMP

USB2_VBUS_SENSE

GPPC_E9_USB2_OC0_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

DESIGN NOTE:

UFS_RESETB

USB2_COMP

USB2_ID

USB2_VBUSSENSE

MPHY_RCOMPN

MPHY_RCOMPP

GPPC_H_12_M2_SKT2_CFG_0

GPPC_H_13_M2_SKT2_CFG_1

GPPC_H_14_M2_SKT2_CFG_2

GPPC_H_15_M2_SKT2_CFG_3

GPPC_E_4_SATA_DEVSLP_0

GPPC_E_5_SATA_DEVSLP_1

GPPC_A_16_USB2_OCB_3_I2S4_SFRM

GPPC_E_9_USB2_OCB_0

GPPC_A_12_SATAXPCIE_1_SATAGP_1_I2S3_SFRM

GPPC_E_0_SATAXPCIE_0_SATAGP_0

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10

USB2P_10

PCIE_1_USB31_1_RXN

PCIE_1_USB31_1_RXP

PCIE_1_USB31_1_TXN

PCIE_1_USB31_1_TXP

PCIE_2_USB31_2_RXN

PCIE_2_USB31_2_RXP

PCIE_2_USB31_2_TXN

PCIE_2_USB31_2_TXP

PCIE_3_USB31_3_RXN

PCIE_3_USB31_3_RXP

PCIE_3_USB31_3_TXN

PCIE_3_USB31_3_TXP

PCIE_4_USB31_4_RXN

PCIE_4_USB31_4_RXP

PCIE_4_USB31_4_TXN

PCIE_4_USB31_4_TXP

PCIE_5_RXN

PCIE_5_RXP

PCIE_5_TXN

PCIE_5_TXP

PCIE_6_RXN

PCIE_6_RXP

PCIE_6_TXN

PCIE_6_TXP

PCIE_7_UFS_00_LAN_0A_TSN_0A_RXN

PCIE_7_UFS_00_LAN_0A_TSN_0A_RXP

PCIE_7_UFS_00_LAN_0A_TSN_0A_TXN

PCIE_7_UFS_00_LAN_0A_TSN_0A_TXP

PCIE_8_UFS_01_LAN_0B_TSN_0B_RXN

PCIE_8_UFS_01_LAN_0B_TSN_0B_RXP

PCIE_8_UFS_01_LAN_0B_TSN_0B_TXN

PCIE_8_UFS_01_LAN_0B_TSN_0B_TXP

PCIE_9_UFS_10_LAN_0C_RXN

PCIE_9_UFS_10_LAN_0C_RXP

PCIE_9_UFS_10_LAN_0C_TXN

PCIE_9_UFS_10_LAN_0C_TXP

PCIE_10_UFS_11_RXN

PCIE_10_UFS_11_RXP

PCIE_10_UFS_11_TXN

PCIE_10_UFS_11_TXP

PCIE_11_SATA_0_TSN_0C_RXN

PCIE_11_SATA_0_TSN_0C_RXP

PCIE_11_SATA_0_TSN_0C_TXN

PCIE_11_SATA_0_TSN_0C_TXP

PCIE_12_SATA_1_TSN_0D_RXN

PCIE_12_SATA_1_TSN_0D_RXP

PCIE_12_SATA_1_TSN_0D_TXN

PCIE_12_SATA_1_TSN_0D_TXP

IN

BI

BI

IN
IN

OUT
OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI

BI

BI

BI

IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

IN
IN

OUT
OUT

OUT
OUT

IN
IN

IN
IN

OUT
OUT

IN
IN

tiger-html.html

RA

CPU : CNV / CSI

CNV_WT_RCOMP MAIN ROUTE TRACE SPACING 200UM

CSI_RCOMP MAIN ROUTE TRACE SPACING 380UM

PLACE RA CLOSE TO PCH

CR-14 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE14

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 14 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4P14

2

1

R7P1

2

1

R6P15

2

1

R6T5

DK25

DM25

DN25

DJ25

DV15

DJ10

DK10

DJ13
DG13
DF15
DF17

DR30

K14

D22

B22
E22

D20

A20
B20

B18
A18

D18

E18

C16
D16

D15

E15
A15
B15

L18

N18

L20

N20

G20

H20

H16

G16
G18

H18

L16

N16

G14

H14

L14

N14

DN51

DK47
DM47
DN49
DR49
DN45
DN47

DU43
DV43
DR44
DT43
DV44
DW44

U5E1

47B5

14C3

29A2

14B4 29A7

46B2

46C1

46A7

46C1

46B1

29A2 14B4

46A7

46A7

46A7
46A7
46A7

46D6
46C6
46C6
46C6

46D6

46C6

14B3

29A7

LPID6529

10 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

150

CH

1/16W

0402LF

1%

5%

0

0 5%

1%

0402LF

CH

1/16W

150

CNV_PA_BLANKING

GPPC_F2_CNV_RGI_DT

GPPC_F0_CNV_BRI_DT

KEYE_CNV_BRI_DT

KEYE_CNV_RGI_DT

CNV_WT_D1_DP

GPPC_F1_CNV_BRI_RSP

GPPC_F3_CNV_RGI_RSP

GPPC_F2_CNV_RGI_DT

CSI_RCOMP

CNV_WT_D0_DP

CNV_WT_D1_DN

CPU : CNV/CSI

CNV_WT_D0_DN
CNV_WT_CLK_DP
CNV_WT_CLK_DN

CNV_WR_D1_DN
CNV_WR_D0_DP
CNV_WR_D0_DN
CNV_WR_CLK_DP

CNV_WR_D1_DP

CNV_WT_RCOMP

CNV_WR_CLK_DN

GPPC_F0_CNV_BRI_DT

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN

GPPC_F_4_CNV_RF_RESET_B

GPPC_F_6_CNV_PA_BLANKING

GPPC_F_5_MODEM_CLKREQ_CRF_XTAL_CLKREQ

GPPC_F_0_CNV_BRI_DT_UART0_RTSB

GPPC_F_1_CNV_BRI_RSP_UART0_RXD

GPPC_F_2_CNV_RGI_DT_UART0_TXD

GPPC_F_3_CNV_RGI_RSP_UART0_CTSB

CNV_WT_RCOMP

CNV_WR_CLKN

CNV_WR_CLKP

CNV_WR_D0N

CNV_WR_D0P

CNV_WR_D1N

CNV_WR_D1P

CNV_WT_CLKN

CNV_WT_CLKP

CNV_WT_D0N

CNV_WT_D0P

CNV_WT_D1N

CNV_WT_D1P

GPPC_D_4_IMGCLKOUT_0_BK_4_SBK_4

GPPC_H_20_IMGCLKOUT_1

GPPC_H_21_IMGCLKOUT_2

GPPC_H_22_IMGCLKOUT_3

GPPC_H_23_IMGCLKOUT_4

CSI_RCOMP_1

CSI_A_D0N_B_D3N

CSI_A_D0P_B_D3P

CSI_A_D1N_B_D2N

CSI_A_D1P_B_D2P

CSI_B_CKN

CSI_B_CKP

CSI_B_D0N

CSI_B_D0P

CSI_B_D1N

CSI_B_D1P

CSI_C_CKN

CSI_C_CKP

CSI_C_D0N

CSI_C_D0P

CSI_C_D1N

CSI_C_D1P

CSI_D_D0N_C_D3N

CSI_D_D0P_C_D3P

CSI_D_D1N_C_D2N

CSI_D_D1P_C_D2P

CSI_E_CKN

CSI_E_CKP

CSI_E_D0N_F_D3N

CSI_E_D0P_F_D3P

CSI_E_D1N_F_D2N

CSI_E_D1P_F_D2P

CSI_F_CKN

CSI_F_CKP

CSI_F_D0N

CSI_F_D0P

CSI_F_D1N

CSI_F_D1P

tiger-html.html

JB

JA

SAVE CMOS - OPEN (DEFAULT)

CLEAR CMOS - SHORT

CLEAR ME RTC REGISTER - SHORT

SAVE ME RTC REGISTER - OPEN (DEFAULT)

JA - SRTC REST_N

JB - RTC REST_N

B2B

M.2 KEY B

B2B

GBE

B2B

GBE

B2B

KEY E

KEY B

CPU : PCIE CLOCK

TP

B2B

M.2 KEY E

CLK_BIASREF MAIN ROUTE TRACE SPACING 150UM TO GND

CR-15 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE15

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 15 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4E1

1

TP6R3

2

1

R3D1

1

TP3D1

1

TP5C1

1

TP5C2

2

1

R4C3

2

1

R1E1

2

1

R1E2

2

1

R2N5

2

1

R8H5

2

1

R7T2

C2C7

R2C5

2

1

R2C2

2

1

R2C1

2

1

C2C6

R2C4

2

1

R7R6

2

1

R4C6

2

1

R4F2

2

1

C4C4

2

1

C4C1

2

1

C3F6

2

1

C3F5

2

4

3

1

Y3C1

2

1

Y3F1

DM1
DL1

DK37

DN37

DT47
DR47

DF23
DG25

DU14

DT24
DT30
DV30
DW30

DW41

BW1

CB2

BW4

CL7

CB4

BY4

CN7

BW2

CB1

BW5

CL8

CB5

BY3

CN8

DJ5

U5E1

64B8

15C4

46B7

48C6

15A5

46B1

64C8
64C8

50C7

15A5

50C7

64B8

64B8

15C4

64B8

46B7

48C6

46B7

48C2

50C7

64C8

64C8

V3P3A_RTC

V3P3_S

LPID6529

11 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPDB

XTAL

GENERIC

K38521-001

32.768KHZ

D71700-094

XTAL
38.4MHZ
+/-20PPM

GENERIC
LPDB

C0G

5%

18PF

25V

0201LF

5%

18PF

25V

0201LF

C0G

15PF

0201LF
50V

5%
C0G

5%
C0G

15PF

0201LF
50V

10M

CH

0402LF

5%

200K 1%

0402LF CH

1K

EMPTY

5%

0402LF
1/16W

0
0
EMPTY
0603LF
50V

6.3V

0402LF

X5R

1UF
20%

1%

20K

CH
0402LF
1/16W

0402LF

1%
CH

1/16W

20K

EMPTY

0

0

0603LF
50V

6.3V

20%
X5R

1UF

0402LF

10K

CH

1/16W

5%

0402LF

CH
0402LF

5%

10K

1/16W

5%

10K

CH

1/16W

0402LF

1/16W

CH

10K

0402LF

5%

10K

0402LF

5%
CH

1/16W

0402LF
1/16W

RESN

1%

60.4

TP

TP

TP

EMPTY

1/16W

0402LF

10K
5%

TP

10K
5%
EMPTY
0402LF
1/16W

CLK_BIASREF

PCIE4_CLK_DN

PCH_XTAL_OUT
PCH_XTAL_IN

SRTC_RST_N

RTC_XTAL_2

PCIE3_P1_CLK_DP

PCIE3_P2_CLK_DN

RTC_RST_N

SUS_CLK

RTC_XTAL_1

CLK_P0_REQ_N

PCIE3_P4_CLK_DP
PCIE3_P4_CLK_DN

PCIE3_P3_CLK_DP

SRTC_RST_N

PCIE3_P3_CLK_DN

PCIE3_P6_CLK_DN

PCIE3_P5_CLK_DN

PCIE3_P5_CLK_DP

RTC_RST_N

PCIE4_CLK_DP

PCIE3_P1_CLK_DN

PCIE3_P2_CLK_DP

PCIE3_P6_CLK_DP

CLK_P1_REQ_N

CLK_P2_REQ_N

CLK_P3_REQ_N

CLK_P4_REQ_N

CLK_P5_REQ_N

CLK_P6_REQ_N

CPU : PCIE CLOCK

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT
OUT

OUT

IN

IN

IN

IN

OUT

SRTCRSTB

RTESTB

RTCX1

RTCX2

GPD_8_SUSCLK

XTAL_IN

XTAL_OUT

GPPC_D_5_SRCCLKREQB_0

GPPC_D_6_SRCCLKREQB_1

GPPC_D_7_SRCCLKREQB_2

GPPC_D_8_SRCCLKREQB_3

GPPC_H_10_SRCCLKREQB_4

GPPC_H_11_SRCCLKREQB_5

GPPC_F_19_SRCCLKREQB_6

CLK_BIASREF

CLKOUT_SRC_N_0_G4

CLKOUT_SRC_P_0_G4

CLKOUT_SRC_N_1

CLKOUT_SRC_P_1

CLKOUT_SRC_N_2

CLKOUT_SRC_P_2

CLKOUT_SRC_N_3_G4

CLKOUT_SRC_P_3_G4

CLKOUT_SRC_N_4_UFS_REF_CLK_1

CLKOUT_SRC_P_4_UFS_REF_CLK_0

CLKOUT_SRC_N_5

CLKOUT_SRC_P_5

CLKOUT_SRC_N_6

CLKOUT_SRC_P_6

T_POINT1

T_POINT1

T_POINT1

T_POINT1

OUT
OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT
OUT

OUT

OUT

OUT

tiger-html.html

PLACE RES CLOSE TO MCP WITHIN 1.5INCH

PLACE CLOSE TO MCP - WITHIN 100MILS

CPU : SYS PWR MANAGEMENT

CR-16 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE16

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 16 OF 80

INTEL CONFIDENTIAL
<>

1

TP6R10

4

5

3

2

1

U8W1

1

TP6R6

2

1

R4F1

1

TP6R12

2

1

R2J4

2

1

C2J1

2

1

R6R8

2

1

R6R12

1

TP6R11

2

1

R6R13

1

TP5P1

2

1

R5N8

2

1

R5N5

2

1

R6N4

2

1

R6N6

2

1

R6T2

R7R7

2

1

R6R11

2

1

R6R14

DK39

CE5
BP8
BP9

DD10

DF10

DT49

DV49

DN39

DM35

DN35

DM37

DN27
DG31

DW12

DR12

DD41

DD42

CW40

DT41

DM43

DT44

DN43

DR41

DJ41
DJ43

DK41

DM41

DK43

DN41

DK35

BM9

U5E1

30B2

78B5

78C1

79C1

78B6

79C3

79B5

65B6

79A5

79B1

38A4

79B8

64B3 79B5 39B7 40C5
47A4 48A4 50C7 52A8

57A7 60A8 63A7

46A7 50C8 57A3

57A3

16A6

16A4

16A4

77A8

16C2

50C7

78C1

29B8

16B3

16A3

79A7

40A3

77A8

16B8

64B3

79A7

60B7

65A1

68A8

69A7

77C6

79A4

65A1

79A5

60B7

66A8

67C8

79C8

16C2

16C2

64B3 79B7 60B7 65A4 69A7 71A7 71B1 75A3 75A8 75C3
75C8 77B8 78B2

16C7

78B5

78C1

16C7

77D4

16C2

60A3

60B7

V3P3A_RTC

V3P3_A

VCCST_TERM

V3P3_A

12 OF 21

LPID6529

SOC

TGL_U_IP

BMAP_REV=1.2

1/16W

CH

10K
1%

0402LF

10K

1/16W

1%

0402LF

CH

CH

5%

0402LF

1M

1/16W

0

0

0402LF CH

CH

0 5%

0402LF

CH

5%

0

0402LF

1K
1%
CH
0402LF
1/16W

5%

62

0402LF CH

EMPTY

10K 1%

0402LF

0 5%

0402LF CH

5%

0

0402LF EMPTY

10%

0402LF

X5R

0.1UF

5%

0

0402LF EMPTY

1%

1K

CH

1/16W

0402LF

IC
C78568-001

TP

SPIVCCIOSEL

INTRUDER_N

PCH_PWROK

SYS_PWROK

DSW_PWROK

SYS_RST_N

PM_SLP_LAN_N

RSMRST_N

PM_PLTRST_N

PM_WAKE_N

GPPC_H3_DEBUG

CPUPWRGD

GPD2_LAN_WAKE_N

GPD_6_SLP_AB

VCCST_PWRGD
VCCST_OVERRIDE

VCCST_PWRGD_TCSS

CPU_C10_GATE_N

VCCST_OVERRIDE

GPD_11_LANPHYPC

SLG_PWRBTN_N

GPD7

ACPRESENT_N

BATLOW_N

PM_PWRBTN_N

PLTRST_N

PM_SLP_S0_N

SLP_WLAN_N

SLP_S3_N

PM_SLP_S4_N

PM_SLP_S5_N

PM_SLP_SUS_N

VCCST_PWRGD_TCSS

VCCST_PWRGD

PM_SLP_S3_N

SLP_S3_N

H_VCCST_PWRGD

PLTRST_N

VCCST_OVERRIDE_R

PM_PWRBTN_N

SLG_PWRBTN_SIO_OUT

CPU : SYS PWR MANAGEMENT

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

IN

OUT

IN

IN

BI

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

IN

OUT

T_POINT1

G

74AHC1G08

V

OUT

IN

OUT

OUT

IN

GPPC_F_21_EXT_PWR_GATE2B

GPPC_F_20_EXT_PWR_GATEB

VCCST_OVERRIDE

VCCST_PWRGD

VCCSTPWRGOOD_TCSS

GPD_7

GPD_11_LANPHYPC_DSWLDO_MON

GPD_2_LAN_WAKEB

WAKEB

GPPC_H_3_SX_EXIT_HOLDOFFB_IEH_FATAL_ERR2B

GPPC_H_18_CPU_C10_GATEB

GPPC_B_11_PMCALERTB

GPD_1_ACPRESENT

GPD_0_BATLOWB

GPD_3_PWRBTNB

CPUPWRGD

SPIVCCIOSEL

INTRUDERB

PCH_PWROK

SYS_PWROK

DSW_PWROK

GPPC_B_13_PLTRSTB

SYS_RESETB

RSMRSTB

SLP_LANB

GPPC_B_12_SLP_S0B

GPD_9_SLP_WLANB

GPD_6_SLP_AB

GPD_4_SLP_S3B

GPD_5_SLP_S4B

GPD_10_SLP_S5B

SLP_SUSB

tiger-html.html

PLACE THE RA CLOSE TO CPU

AND BREAKOUT AS 2 TRACES

AND BREAKOUT AS 2 TRACES

PLACE THE RA CLOSE TO CPU

RA

RB

RA

RA

CPU POWER : VCCIN

CPU

AND BREAKOUT AS 2 TRACES

PLACE THE RA CLOSE TO CPU

VR

RB

SVID

RB

CR-17 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE17

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 17 OF 80

INTEL CONFIDENTIAL
<>

2

1

R1T8

2

1

R4N10

2

1

R1T10

2

1

R4N13

2

1

R4N14

2

1

R9F11

2

1

R9F8

2

1

R4N8

2

1

R9F9

2

1

R4N12

2

1

R4N9

2

1

R1T9

R37

M12
M11
P12

R38

W32

W28

W24

W22

V33

V31

V29

V27

V25

V23

U33

U31

U29

U27

U23

T31

T27

T25

T23

T21

P32

P30

P28

P26

P24

N32

N30

N26

N24

L32

L30

L26

L24

K32

K30

K26

K24

K2

K1

J2

J1

H32

H30

H26

H24

G32

G30

G26

G24

G2

E33

E32

E30

E29

E27

E26

E24

D35

D33

D30

D29

D26

D24

CB12

CA10

BY12

BV12

BU40

BU10

BT39

BT12

BR40

BR10

BP39

BP12

BN40

BM39

BL40

BL10

BK39

BJ40

BJ10

BH9

BH39

BH12

BG40

BG10

BF9

BE40

BE10

BD9

BD39

BC40

BC10

BB9

BB39

BA40

BA10

B35

B33

B30

B29

B26

B24

AY39

A35

A33

A30

A29

A26

A24

U5E1

17A6

72C1

17B5

17A5

17C5

72C1

17A6

17A6

72C6

72C6

72B6

VCCSTG_TERM

VCCIN

VCCIN

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

LPID6529

13 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

1%

100

0402LF
1/16W

CH

0402LF
1/16W

1%

100

CH

CH

0 5%

0402LF

CH

0 5%

0402LF

CH

5%

0402LF
1/16W

56

CH

5%

0402LF

0

CH

0 5%

0402LF

0402LF

5%

CH

0

CH

0 5%

0402LF

5%

43

0402LF
1/16W

CH

5%

43

EMPTY

1/16W

0402LF

1/16W

110
1%
EMPTY
0402LF

VCCIN_VIDSOUT

VCC_VCCIN_SENSE_P

VR_SVID_CLK_R

PLACE THE RB CLOSE TO VR

PLACE THE RB CLOSE TO VR

CPU : VCCIN

VCCIN_VIDALERT_N

VCCIN_VIDSCK

VCCIN_VIDSOUT

VCC_VCCIN_SENSE_N

VCCIN_VIDSCK

VCCIN_VIDALERT_N

VR_SVID_DATA

VR_SVID_DATA_R

VR_SVID_CLK

PLACE THE RB CLOSE TO VR

VR_SVID_ALERT_R_N

VR_SVID_ALERT_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

BI

BI

VIDALERTB

VIDSCK

VIDSOUT

VSSIN_SENSE

VCCIN_SENSE

VCCIN_111

VCCIN_110

VCCIN_109

VCCIN_108

VCCIN_107

VCCIN_106

VCCIN_105

VCCIN_104

VCCIN_103

VCCIN_102

VCCIN_101

VCCIN_100

VCCIN_99

VCCIN_98

VCCIN_97

VCCIN_96

VCCIN_95

VCCIN_94

VCCIN_93

VCCIN_92

VCCIN_91

VCCIN_90

VCCIN_89

VCCIN_88

VCCIN_87

VCCIN_86

VCCIN_85

VCCIN_84

VCCIN_83

VCCIN_82

VCCIN_81

VCCIN_80

VCCIN_79

VCCIN_78

VCCIN_77

VCCIN_76

VCCIN_75

VCCIN_74

VCCIN_73

VCCIN_72

VCCIN_71

VCCIN_70

VCCIN_69

VCCIN_68

VCCIN_67

VCCIN_66

VCCIN_65

VCCIN_64

VCCIN_63

VCCIN_62

VCCIN_61

VCCIN_60

VCCIN_59

VCCIN_58

VCCIN_57

VCCIN_56

VCCIN_55

VCCIN_54

VCCIN_53

VCCIN_52

VCCIN_51

VCCIN_50

VCCIN_49

VCCIN_48

VCCIN_47

VCCIN_46

VCCIN_45

VCCIN_44

VCCIN_43

VCCIN_42

VCCIN_41

VCCIN_40

VCCIN_39

VCCIN_38

VCCIN_37

VCCIN_36

VCCIN_35

VCCIN_34

VCCIN_33

VCCIN_32

VCCIN_31

VCCIN_30

VCCIN_29

VCCIN_28

VCCIN_27

VCCIN_26

VCCIN_25

VCCIN_24

VCCIN_23

VCCIN_22

VCCIN_21

VCCIN_20

VCCIN_19

VCCIN_18

VCCIN_17

VCCIN_16

VCCIN_15

VCCIN_14

VCCIN_13

VCCIN_12

VCCIN_11

VCCIN_10

VCCIN_9

VCCIN_8

VCCIN_7

VCCIN_6

VCCIN_5

VCCIN_4

VCCIN_3

VCCIN_2

VCCIN_1

IN

OUT

OUT

OUT

OUT

BI

BI

BI

BI

tiger-html.html

CPU POWER: VDD2_MEM/VCCSTG/VCCST

CAD NOTE: CLOSE TO BGA

CR-18 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE18

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 18 OF 80

INTEL CONFIDENTIAL
<>

1

TP4P4

1

TP4P8

1

TP4P6

2

1

C4N1

2

1

C5N3

2

1

C4N6

2

1

C4N5

2

1

R5N4

2

1

R4N15

2

1

R4N21

2

1

R4N16

2

1

R5C5

AF12
AD12

M9

AF9

BP4

BP2
BP1

BT4

BT2
BT1

V15

AN10
AM9
AG10

T52

T51

F49

E51

D50

CR40

CP47

CN40

CL40

CJ40

CH39

CG40

CE40

CC50

CC49

CC40

CA40

BV52

BV51

BK52

BK51

BD52

BD51

AW52

AW51

AW40

AU40

AT52

AR39

AP40

AN39

AM40

AL39

AK52

AK51

AK40

AJ39

AH40

AG39

AF40

AE39

AD52

AD51

AD40

AC39

AB40

AA39

U5E1

VCCSTG_FUSE

VCCST

VCCSTG

VCCSTG_FUSE

VCCSTG

VCCSTG_FUSE

VCCSTG_OUT_FUSE

VCCFPGM

VCCST_TERM

VCCSTG_TERM

VCCST

VCCSTG_OUT_LGC

VDDQ_MEM

VCCSTG_OUT_LGC

VCCION_OUT

VCCFPGM

VCCSTG_OUT_FUSE

LPID6529

TGL_U_IP

BMAP_REV=1.2

15 OF 21

SOC

EMPTY

0

0603LF

0

CH

0603LF

0.01 1%

CH

0603LF

0.01 1%

CH

0603LF

0.01 1%

CH

0603LF

0.01 1%

10V

X5R
0201LF

1UF
20%

1UF

10V

0201LF

X5R

20%

10V

20%

1UF

0201LF

X5R

10V

20%

0201LF

X5R

1UF

TP

TP

TP

CPU : CPU POWER

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

T_POINT1

T_POINT1

T_POINT1

VCCSTG_3

VCCSTG_1

VCCSTG_2

VCCST_3

VCCST_1

VCCST_2

VCCSTG_OUT_LGC

VCCION_OUT

VCCFPGM0

VCCFPGM1

VCCFPGM2

VCCSTGFUSE_1

VCCSTGFUSE_2

VCCSTG_OUT_FUSE

VCCDD2_47

VCCDD2_46

VCCDD2_45

VCCDD2_44

VCCDD2_43

VCCDD2_42

VCCDD2_41

VCCDD2_40

VCCDD2_39

VCCDD2_38

VCCDD2_37

VCCDD2_36

VCCDD2_35

VCCDD2_34

VCCDD2_33

VCCDD2_32

VCCDD2_31

VCCDD2_30

VCCDD2_29

VCCDD2_28

VCCDD2_27

VCCDD2_26

VCCDD2_25

VCCDD2_24

VCCDD2_23

VCCDD2_22

VCCDD2_21

VCCDD2_20

VCCDD2_19

VCCDD2_18

VCCDD2_17

VCCDD2_16

VCCDD2_15

VCCDD2_14

VCCDD2_13

VCCDD2_12

VCCDD2_11

VCCDD2_10

VCCDD2_9

VCCDD2_8

VCCDD2_7

VCCDD2_6

VCCDD2_5

VCCDD2_4

VCCDD2_3

VCCDD2_2

VCCDD2_1

tiger-html.html

CLOSE TO BGA

HDA: V3P3_A(DEFAULT)

AS PER PI FEEBACK

CAP ADDED FOR PI SIMULATION

DESIGN NOTE:

PCH POWER : VCCIN_AUX/VNN/1.05V/1.8V/3.3V

I2S: V1P8_A

CLOSE TO BGA

CLOSE VCCPRIM_1P8 PIN

CR-19 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE19

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 19 OF 80

INTEL CONFIDENTIAL
<>

2

1

L7P1

2

1

C6P9

2

1

C6P8

2

1

R7R1

2

1

R7P10

2

1

R6T8

2

1

R7R5

2

1

R6R7

2

1

R6R6

2

1

C5N5

2

1

C6R4

2

1

C7R4

2

1

C7R5

2

1

C6R6

2

1

C6R8

2

1

C7P1

2

1

R7P3

2

1

R7P4

2

1

R7R8

2

1

R7R2

2

1

C6R3

2

1

C6R2

2

1

C6P6

2

1

R6P14

2

1

R7P5

2

1

C4N4

2

1

R4N11

1

TP6R9

1

TP5N1

1

TP6R1

1

TP6R5

1

TP4P7

1

TP4F1

1

TP6R7

2

1

C4E2

2

1

C4E1

2

1

C6P5

2

1

C6P4

DV34

DC35

DC33
DC31

DD30

DC30

DC28

DA35

DV22

DD22

DD20

DC26

DC24

DC22

DC20

DC18

DA26

DA24

DA22

DA20

DA18

CY26

CY24

CY20

CY18

DA28

CY33

CY31

CV39

DD37

DV46

AK1

AV9

AT9

CY1

CU12

CT10

CR12

CP10

CP1

CM10

CL12

CK10

CJ12

CJ1

CH10

CG12

CF10

CD12

CC1

BY39

BW40

BV39

BV1

AW10

AU10

AT12

AR10

AK2

AE10

AC10

AB12

DD38

DV28

AP12

DV16
DC15

DD18

DD17

DA17

DA15

DA31

BT5

BR4

BR3

DT12

DV12

DB39

DB38

DB37

U5E1

0603LF X5R

0402LF CH

0 0

V1P8A_R

V1P05_OUT_FET

0603LF

VCCDSW_3P3

CH

VCCA_CLKLDO_1P8

10V

V1P8_A

X5R

20%
X5R
0201LF

0603LF

0 1A

EMPTY

30%

2.7A

J65894-001

47UF

VLDOSTD_OUT_0P85

0.68UH

VPHY_1P24

V1P8_A

V3P3_A

VPGPPR_1P8_3P3

0201LF

0

0

20%

V1P05_OUT_PCH

CPU : PCH POWER

1UF

10V

10V

X5R

20%

0201LF

VCCIN_AUX_VCCSENS

VNN_CTRL

VCCIN_AUX_VSSSENS

GPPC_B2_PROCHOT_N_R

X5R

VCCIN_AUX_CORE_VID1_R

VCCIN_AUX_CORE_VID0_R

VCCIN_AUX_CORE_VID1

VCCIN_AUX_CORE_VID0

V1P05_CTRL

GPPC_B2_PROCHOT_N

20%

1UF

0201LF

CH

0603LF

0 1A

EMPTY

0603LF

0 0

0

CH

5%

0402LF

CH

0402LF

0

CH

5%

0 5%

0402LF CH

X5R

20%

1UF

0201LF
10V

1UF
20%
X5R

10V

X5R

10%

0.1UF

0402LF

0201LF
10V

20%

1UF

X5R

0402LF

X5R

20%

6.3V

1A

0

0603LF CH

0603LF CH

1%

0.01

0201LF

X5R

10V

1UF
20%

10V

10%
X5R
0402LF

0.1UF

10V

0201LF

1UF

X5R

20%

1%
EMPTY
0402LF

100K

1/16W

1/16W

EMPTY

100K
1%

0402LF

0402LF

X5R

20%

10UF

6.3V

0603LF CH

1%

0.01

TP

TP

TP

TP

0402LF

X5R

0.1UF

6.3V

X5R

20%

4.7UF

SOC

14 OF 21

LPID6529

BMAP_REV=1.2

TGL_U_IP

VCCIN_AUX

VCCIN_AUX_FIL

VCCIN_AUX

VPHY_1P24

VNN_EXT

V1P05_EXT

V1P05_EXT

VNN_EXT

V3P3A_RTC

VCCIN_AUX_FIL

V3P3_A

VCCPFUSE_3P3

VDSW_1P05

V3P3A_RTC

V1P05_OUT_FET

VRTC_EXT

V1P8_A

V3P3_A

VPGPPR_1P8_3P3

VCCPFUSE_1P8

V1P8_A

22UF

VLDOSTD_OUT_0P85

V1P05_OUT_PCH

0402LF

10%

VDSW_1P05

10V

0201LF

X5R

20%

1UF

1UF

10V

20%

1UF

0201LF

V3P3_A

VCCDSW_3P3

V1P8_A

V1P8_A

10V

VCCPFUSE_1P8

70A1

71A7

70A1

70B7 70A6

70B7 70A8

71C8

22C8

VRTC_EXT

V1P8_A

6.3V

V3P3_A

TP

VCCPFUSE_3P3

TP

TP

VCCANA_EHV

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

DESIGN NOTE:

CAD NOTE:

CAD NOTE:

OUT

OUT

IN

VCCANA_EHV

VCCPFUSE_1P8

VCCPFUSE_3P3_2

VCCPFUSE_3P3_1

VCCPGPPR

VCCPDSW_3P3

VCCPRTC_3P3

VCCPRIM_CNVLDO_1P05

VCCPRIM_FUSE_1P05

VCC1P05_OUT_PCH

VCC1P05_OUT_FET_3

VCC1P05_OUT_FET_2

VCC1P05_OUT_FET_1

VCCDSW_1P05

VCCDPHY_1P24

VCCA_CLKLDO_1P8_1

VCCA_CLKLDO_1P8_2

VCCLDOSTD_OUT_0P85

VCCRTCEXT

VCCPRIM_3P3_4

VCCPRIM_3P3_3

VCCPRIM_3P3_2

VCCPRIM_3P3_1

VCCPRIM_1P8_17

VCCPRIM_1P8_16

VCCPRIM_1P8_15

VCCPRIM_1P8_14

VCCPRIM_1P8_13

VCCPRIM_1P8_12

VCCPRIM_1P8_11

VCCPRIM_1P8_10

VCCPRIM_1P8_9

VCCPRIM_1P8_8

VCCPRIM_1P8_7

VCCPRIM_1P8_6

VCCPRIM_1P8_5

VCCPRIM_1P8_4

VCCPRIM_1P8_3

VCCPRIM_1P8_2

VCCPRIM_1P8_1

GPPC_B_1_CORE_VID_1

GPPC_B_0_CORE_VID_0

GPPC_F_23_V1P05_CTRL_IEH_NONFATAL_ERR1B

GPPC_F_22_VNN_CTRL_IEH_CORR_ERR0B

GPPC_B_2_VRALERTB

VCC_V1P05EXT_1P05_2

VCC_V1P05EXT_1P05_1

VCC_VNNEXT_1P05_2

VCC_VNNEXT_1P05_1

VCCIN_AUX_VCCSENSE

VCCIN_AUX_VSSSENSE

VCCINAUX_FIL

VCCIN_AUX_28

VCCIN_AUX_27

VCCIN_AUX_26

VCCIN_AUX_25

VCCIN_AUX_24

VCCIN_AUX_23

VCCIN_AUX_22

VCCIN_AUX_21

VCCIN_AUX_20

VCCIN_AUX_19

VCCIN_AUX_18

VCCIN_AUX_17

VCCIN_AUX_16

VCCIN_AUX_15

VCCIN_AUX_14

VCCIN_AUX_13

VCCIN_AUX_12

VCCIN_AUX_11

VCCIN_AUX_10

VCCIN_AUX_9

VCCIN_AUX_8

VCCIN_AUX_7

VCCIN_AUX_6

VCCIN_AUX_5

VCCIN_AUX_4

VCCIN_AUX_3

VCCIN_AUX_2

VCCIN_AUX_1

OUT
OUT

OUT
OUT

T_POINT1

T_POINT1

T_POINT1

T_POINT1

T_POINT1

T_POINT1

T_POINT1

tiger-html.html

CPU : CORE GND

CR-20 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE20

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 20 OF 80

INTEL CONFIDENTIAL
<>

Y8

Y50

Y49

Y4

W48

W47

W45

W44

W42

W41

W39

W30

W26

W16

W1

V8

V4

V19

U49

U39

U25

U19

T8

T48

T4

T33

T29

T19

R44

R39

P8

P49

P4

P35

P33

P22

P20

P18

P16

P14

P11

N48

N41

N39

N34

N28

N22

M50

M2

M1

L49

L47

L45

L44

L42

L41

L39

L34

L28

L22

K5

K48

K34

K28

K22

K20

K18

K16

J49

J39

H8

H34

H28

H22

H12

G52

G51

G48

G39

G34

G28

G22

E48

E35

E19

E13

DW51

DV52

DV40

DV1

DU46

DU40

DU34

DU28

DU22

DU16

DU11

DT50

DT4

DR46

DR40

DR34

DR28

DR22

DR16

DR11

DP53

U5E1

DN2

DN1

DM45

DM4

DM39

DM33

DM27

DM21

DM15

DM10

DL5

DL3

DK51

DJ4

DJ2

DJ1

DG6

DG53

DG5

DG45

DG39

DG33

DG27

DG21

DG15

DF37

DF19

DE5

DE3

DD52

DD51

DD45

DD39

DD35

DD33

DD31

DD28

DD26

DD24

DD15

DC17

DA53

DA33

DA30

D5

D49

D42

D36

D32

D27

CY5

CY47

CY45

CY44

CY42

CY41

CY35

CY22

CY17

CV52

CV51

CV5

CV48

CV10

CU9

CU4

CT5

CR9

CR53

CR48

CP5

CP45

CP44

CP42

CP41

CP3

CN9

CN52

CN51

CN48

CN12

CL9

CK53

CK48

CK39

CJ9

CJ5

CJ3

CH47

CH45

CH44

CH42

CH41

CG9

CG52

CG51

CG48

CE49

CD7

CD48

CD44

CC5

CC3

CC10

CB41

CA48

C23

C19

C13

BY9

BY49

BY47

BY45

BY44

U5E1

BY42

BY41

BW10

BV5

BV48

BV3

BU49

BT48

BT44

BP7

BP50

BP5

BP49

BP41

BN48

BM8

BM47

BM45

BM44

BM42

BM41

BM4

BM1

BL49

BK8

BK48

BK4

BK12

BH8

BH4

BH2

BH1

BG53

BG48

BF8

BF7

BF5

BF47

BF45

BF44

BF42

BF41

BF4

BF39

BD8

BD48

BD4

BD12

BC2

BC1

BB8

BB4

BA53

BA48

B8

B52

B48

B42

B39

B36

B32

B27

B23

B2

B19

B13

AY9

AY8

AY47

AY45

AY44

AY42

AY41

AY4

AW48

AW2

AW1

AV8

AV7

AV5

AV4

AV39

AV12

AT8

AT51

AT48

AT4

AP8

AP4

AN53

AN48

AN47

AN45

AN44

AN42

AN41

AM8

AM4

AM2

AM1

AK8

AK7

AK5

AK48

AK4

AK12

AH8

AH4

AG53

AG48

AG47

AG45

AG44

AG42

AG41

AF8

AF4

AD8

AD48

AD4

AC49

AC44

AB8

AB7

AB5

AA48

AA41

A49

A45

A32

A27

U5E1

16 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

17 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

LPID6529

BMAP_REV=1.2

TGL_U_IP

SOC

18 OF 21

CPU : GND

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

VSS_245

VSS_244

VSS_243

VSS_242

VSS_241

VSS_240

VSS_239

VSS_238

VSS_237

VSS_236

VSS_235

VSS_234

VSS_233

VSS_232

VSS_231

VSS_230

VSS_229

VSS_228

VSS_227

VSS_226

VSS_225

VSS_224

VSS_223

VSS_222

VSS_221

VSS_220

VSS_219

VSS_218

VSS_217

VSS_216

VSS_215

VSS_214

VSS_213

VSS_212

VSS_211

VSS_210

VSS_209

VSS_208

VSS_207

VSS_206

VSS_205

VSS_204

VSS_203

VSS_202

VSS_201

VSS_200

VSS_199

VSS_198

VSS_197

VSS_196

VSS_195

VSS_194

VSS_193

VSS_192

VSS_191

VSS_190

VSS_189

VSS_188

VSS_187

VSS_186

VSS_185

VSS_184

VSS_183

VSS_182

VSS_181

VSS_180

VSS_179

VSS_178

VSS_177

VSS_176

VSS_175

VSS_174

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_166

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_156

VSS_155

VSS_154

VSS_153

VSS_152

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_146

VSS_145

VSS_144

VSS_143

VSS_142

VSS_141

VSS_140

VSS_139

VSS_138

VSS_137

VSS_136

VSS_135

VSS_134

VSS_133

VSS_132

VSS_131

VSS_130

VSS_129

VSS_128

VSS_127

VSS_126

VSS_125

VSS_124

VSS_123

VSS_122

VSS_121

VSS_120

VSS_119

VSS_118

VSS_117

VSS_116

VSS_115

VSS_114

VSS_113

VSS_112

VSS_111

VSS_110

VSS_109

VSS_108

VSS_107

VSS_106

VSS_105

VSS_104

VSS_103

VSS_102

VSS_101

VSS_100

VSS_99

VSS_98

VSS_97

VSS_96

VSS_95

VSS_94

VSS_93

VSS_92

VSS_91

VSS_90

VSS_89

VSS_88

VSS_87

VSS_86

VSS_85

VSS_84

VSS_83

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_71

VSS_70

VSS_69

VSS_68

VSS_67

VSS_66

VSS_65

VSS_64

VSS_63

VSS_62

VSS_61

VSS_60

VSS_59

VSS_58

VSS_57

VSS_56

VSS_55

VSS_54

VSS_53

VSS_52

VSS_51

VSS_50

VSS_49

VSS_48

VSS_47

VSS_46

VSS_45

VSS_44

VSS_43

VSS_42

VSS_41

VSS_40

VSS_39

VSS_38

VSS_37

VSS_36

VSS_35

VSS_34

VSS_33

VSS_32

VSS_31

VSS_30

VSS_29

VSS_28

VSS_27

VSS_26

VSS_25

VSS_24

VSS_23

VSS_22

VSS_21

VSS_20

VSS_19

VSS_18

VSS_17

VSS_16

VSS_15

VSS_14

VSS_13

VSS_12

VSS_11

VSS_10

VSS_9

VSS_8

VSS_7

VSS_6

VSS_5

VSS_4

VSS_3

VSS_2

VSS_1

VSS_352

VSS_351

VSS_350

VSS_349

VSS_348

VSS_347

VSS_346

VSS_345

VSS_344

VSS_343

VSS_342

VSS_341

VSS_340

VSS_339

VSS_338

VSS_337

VSS_336

VSS_335

VSS_334

VSS_333

VSS_332

VSS_331

VSS_330

VSS_329

VSS_328

VSS_327

VSS_326

VSS_325

VSS_324

VSS_323

VSS_322

VSS_321

VSS_320

VSS_319

VSS_318

VSS_317

VSS_316

VSS_315

VSS_314

VSS_313

VSS_312

VSS_311

VSS_310

VSS_309

VSS_308

VSS_307

VSS_306

VSS_305

VSS_304

VSS_303

VSS_302

VSS_301

VSS_300

VSS_299

VSS_298

VSS_297

VSS_296

VSS_295

VSS_294

VSS_293

VSS_292

VSS_291

VSS_290

VSS_289

VSS_288

VSS_287

VSS_286

VSS_285

VSS_284

VSS_283

VSS_282

VSS_281

VSS_280

VSS_279

VSS_278

VSS_277

VSS_276

VSS_275

VSS_274

VSS_273

VSS_272

VSS_271

VSS_270

VSS_269

VSS_268

VSS_267

VSS_266

VSS_265

VSS_264

VSS_263

VSS_262

VSS_261

VSS_260

VSS_259

VSS_258

VSS_257

VSS_256

VSS_255

VSS_254

VSS_253

VSS_252

VSS_251

VSS_250

VSS_249

VSS_248

VSS_247

VSS_246

tiger-html.html

RVP: VSS_1

CPU : XDP / FIVR DEBUG

CR-21 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE21

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 21 OF 80

INTEL CONFIDENTIAL
<>

1

TP4P5

1

TP4P9

2

1

R7C2

DU1
DT2

DW5

BN10

W34

BM12

V35

DD13

DF13

AR2

AL10

AH12

AM12

AJ10

AR1

D52

DW2
DV2

C1
D2

E1
F1

DV4
DW3

DW6
DV6

T15

V17

U15

K11
K12

K9

T17

K7

H7

K8

H9

E6

H5

E9

D9

E7

B5

U17
H11

Y1

M4

AB4

Y2

A3
B3

DV51
DW52
DV53

A51
B51

AB2

CP39
CU40
AK9

AH9

DR53

DR1
DR2

U5E1

DF50
DF49

CY28

CY30
CY15

DF52

DF53

DT52

DU53

C53
T35
E53
CF39
U35
F53
B53
AP9
A52

BF12
V21
W20
U37
CD39
U21
CB39
BB12
W37
AY12
W38
U38

A6
A4

D4

U5E1

79A4

26C6
26D6

26B6

26B6

26A6

26D4

26D3

26C3

26B3

26B2

26A2

27C7

27B7

27A7

27B4

27A5

19 OF 21

SOC

TGL_U_IP

BMAP_REV=1.2

LPID6529

BMAP_REV=1.2

TGL_U_IP

SOC

20 OF 21

LPID6529

CH

1%

0402LF

49.9

1/16W

TP
TP

NOA_STB_P_0

SKTOCC_N

NOA_RCOMP

CPU : XDP/FIVR DEBUG

NOA_STB_P_1

XDP_NOA1_N

XDP_NOA0_N

XDP_NOA2_N

XDP_NOA3_N

XDP_NOA4_N

XDP_NOA5_N

XDP_NOA6_N

XDP_NOA7_N

XDP_NOA8_N

XDP_NOA9_N

XDP_NOA10_N

XDP_NOA11_N

XDP_NOA12_N

XDP_NOA13_N

XDP_NOA14_N

XDP_NOA15_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

SKTOCC_N

THERMDA

THERMDC

FPF_LDOMON

FPF_MON

FPF_VREF

USB2PLL_HPLDO_MON

CNVLDO_MON

CKPLL_MON*

CKPLL_MON_P

DDIA_OBS

PCIE4_COM0_DFX_DAMON_OBSN_LV

PCIE4_COM0_DFX_DAMON_OBSP_LV

SATA_PLLOBSN

SATA_PLLOBSP

USB31_PLLOBSN

USB31_PLLOBSP

PCIE3_PLLOBSN

PCIE3_PLLOBSP

PCH_EDM1

PCH_EDM2

CPU_EDM_0

CPU_EDM_1

CPU_POPIO_VIEW_0

CPU_POPIO_VIEW_1

PEG_VIEW2

PEG_VIEW3

DDR_VIEW_0

DDR_VIEW_1

TD_ANODE

TD_CATHODE

THERMDA_GT

THERMDC_GT

TCP0_DFX_AMON_OBS_LV

TCP0_DFX_DMONOBS_N_LV0

TCP0_DFX_DMONOBS_P_LV0

TCP0_DFX_DMONOBS_N_LV1

TCP0_DFX_DMONOBS_P_LV1

TCP0_DFX_RCOMP_OBS_LV

HVM_CLK*

HVM_CLK_P

MBPB_0

MBPB_1

MBPB_2

MBPB_3

NOA_AVRB_STB_P_0

NOA_AVRB_STB_P_1

NOA_RCOMP

NOAB_0

NOAB_1

NOAB_2

NOAB_3

NOAB_4

NOAB_5

NOAB_6

NOAB_7

NOAB_8

NOAB_9

NOAB_10

NOAB_11

NOAB_12

NOAB_13

NOAB_14

NOAB_15

OUT

T_POINT1

T_POINT1

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

PCHFIVR_VLOAD_VNNAON

FIVR_VLOAD_CCF

FIVR_VLOAD_CORE0

FIVR_VLOAD_CORE1

FIVR_VLOAD_CORE2

FIVR_VLOAD_CORE3

FIVR_VLOAD_GT

FIVR_VLOAD_SA

FIVR_VLOAD_VCCDDQ

FIVR_VLOAD_VCCIOE

FIVR_VLOAD_VCCION

FIVR_VLOAD_VCCPCIE

FIVR_VLOAD_VCCTCPHY

FIVR_VTARGET_CCF

FIVR_VTARGET_CORE

FIVR_VTARGET_GT

FIVR_VTARGET_PCIE

FIVR_VTARGET_SA

FIVR_VTARGET_TCSS

FIVR_VTARGET_VCCIOE

FIVR_VTARGET_VCCION

FIVR_VTARGET_VDDQ

FIVR_PROBE_ANA_0

FIVR_PROBE_ANA_1

EXTBGREF

PCHFIVR_VLOAD_1P05

PCHFIVR_VLOAD_VNN

PCHFIVR_VTARGET_1P05

PCHFIVR_VTARGET_VNN

PCHFIVR_ANAPB0

PCHFIVR_ANAPB1

PCHFIVR_REFCLK

PCHFIVR_EXTBGREF

tiger-html.html

NC

CPU : JTAG/MISC

PLACE CLOSE TO MCP

WITHIN 1 INCH

MAIN ROUTE TRACE SPACING 300UM

CPU_POPI_RCOMP & PCH_OPI_RCOMP

CPU+PCH JTAG TP

CR-22 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE22

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 22 OF 80

INTEL CONFIDENTIAL
<>

2

1

R5N7

2

1

R6T7

1

2

CR6T1

1

TP4P1

1

TP7D2

1

TP3P3

2

1

R3P7

2

1

R4N7

2

1

R5C4

2

1

R4N17

2

1

R7D6

2

1

R3P10

2

1

R7D3

2

1

R7D2

1

TP7C2

2

1

R7D5

2

1

R3P9

2

1

R3P13

2

1

R3P14

1

TP3P2

2

1

R3P8

2

1

R3P12

1

TP3P1

2

1

R3P15

2

1

R3P11

1

TP7C1

2

1

R7C1

2

1

R7C5

2

1

R7C4

2

1

R7D4

1

TP7D1

2

1

R7D1

2

1

R7C3

2

1

R4N4

1

TP4N1

2

1

R4N2

2

1

R4N3

2

1

R4N6

2

1

R4N5

2

1

R4N18

2

1

R6R10

2

1

R5P1

2

1

R6P13

M5

E2

C11
D11

BK9

CB9

CW12

CM39

D8
A9
E12
B12
A7
H4

DJ27

DF31

DV32

DW32

DT14

DR15

DT15

DF8

DU5

DB42
DB41

G1

DF4

CT39

K4
B9
D12
A12
B6

M7

U5E1

46C1

19B8

22D7 72A3 72B2

22D2

22D8

30A8

22C6 72A3 72B2

22A3

22A5

22B3

60A4

60B3

28A2

22B8

22D5

30C2

22D2

22D2

22C2

22C2

22D2

22D2

22C2

22C2

30A6

22A3

30A7

29A5

22B3

22A8

22A8

22A5

22B8

22A5

22B5

22A8

22C2

22D2

22D2

22C2

VCCSTG_TERM

VCCSTG_TERM

VCCSTG

V3P3_A

VCCSTG_TERM

VCCSTG_TERM

VCCSTG_TERM

VCCST_TERM

SOC

BMAP_REV=1.2

LPID6529

TGL_U_IP

21 OF 21

CH

1%

75K

0402LF

1%
CH

49.9

1/16W

0402LF

CH

1%

1/16W

0402LF

49.9

CH

1%

49.9

1/16W

0402LF

0402LF

499

CH

1%

1%

1K

0402LF

CH

1/16W

CH

5%

0

0201LF

0

0201LF CH

5%

5%
EMPTY

51

0402LF
1/16W

CH

51
5%

1/16W

0402LF

0 5%

CH

0201LF

0201LF

0 5%

CH

EMPTY

1/16W

51
5%

0402LF

5%

51

1/16W

EMPTY
0402LF

0 5%

CH

0201LF

1%
CH

1/16W

0402LF

100

5%

0

0201LF CH

0201LF

0

CH

5%

CH
0402LF

100
1%

1/16W

5%

0

CH

0201LF

0201LF

5%

0

CH

0402LF

5%

51

CH

1/16W

0402LF

5%

51

CH

1/16W

0201LF

0 5%

CH

0201LF CH

0 5%

EMPTY

51
5%

0402LF
1/16W

0402LF

EMPTY

1/16W

5%

51

1%
CH
0402LF

1K

1/16W

1/16W

5%

1K

0402LF

CH

EMPTY

5%

1K

0402LF
1/16W

CH

51
5%

1/16W

0402LF

1N5819HW

SMLF

DIO

D55839-001

5%

0402LF

CH

1/16W

100K

CH

0402LF

43 5%

JTAG_TDO

GPPC_H19

PECI

GPPC_B2_PROCHOT_N

H_PROCHOT_N

CPU_JTAG_TCK

PROCHOT_CPU_N
THRMTRIP_N

CPU_POPI_RCOMP
PCH_OPI_RCOMP

GPPC_H2

H_PROCHOT_N

CPU_JTAG_TMS

PCH_JTAG_TDO

PRDY_N

SIO_PECI

DBG_PMODE

CATERR_N

CPU_JTAG_TCK

PROCHOT_CPU_N

GPPC_F7

CPU_JTAG_TDO

CPU : JTAG/MISC

CPU_EAR_N

CPU_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TDI

JTAG_TDI

CPU_JTAG_TMS

PCH_JTAG_TMS

JTAG_TMS

PRDY_N

PREQ_N

GPPC_H0

JTAG_TCK

PCH_JTAG_TMS

GPPC_H1

GPPC_F9

GPPC_F10

PREQ_N

PCH_JTAG_TRST_N

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAGX

CPU_JTAG_TDI

CPU_JTAG_TDO

CPU_JTAG_TRST_N

JTAG_TCK1

PCH_JTAG_TRST_N

JTAG_TRST_N

PCH_JTAGX

CPU_JTAG_TRST_N

PCH_JTAG_TCK

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

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D

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3

4

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7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

BI

GPPC_F_10

GPPC_F_9_BOOTMPC

GPPC_F_7

EAR_N

PRDYB

PREQB

PCH_CPU_TRSTB

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAGX

CPU_JTAG_TCK

CPU_JTAG_TDI

CPU_JTAG_TDO

CPU_JTAG_TMS

CPU_JTAG_TRSTB

GPPC_H_19_TIME_SYNC_0

GPPC_H_0

GPPC_H_1

GPPC_H_2

GPPC_E_3_CPU_GP_0

GPPC_E_7_CPU_GP_1

GPPC_B_3_CPU_GP_2

GPPC_B_4_CPU_GP_3

DBG_PMODE

PCH_OPIICCCTL

PCH_OPIICCOBS

PCH_OPIRCOMP

CPU_POPIRCOMP

THRMTRIPB

PROCHOTB

PECI

CATERRB

BI

OUT

tiger-html.html

SECONDARY BSC

PACKAGE EDGE > 0402 CAPS > 0805 CAPS > BULK CAPS >VR POWER

COMPONENT PLACEMENT ORDER:

PRIMARY TSC

CORE PWR DECOUPLE : VCCIN

EMC CAPS - PLACE <5MM FROM SOC VCCIN

EMC CAPS

CR-23 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE23

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 23 OF 80

INTEL CONFIDENTIAL
<>

2

1

C4P6

2

1

C4R7

2

1

C4P3

2

1

C4R9

2

1

C4R10

2

1

C4R8

2

1

C4P4

2

1

C4P7

2

1

C4P5

2

1

C4R11

2

1

C4R4

2

1

C5R1

2

1

C4P1

2

1

C5P8

2

1

C4P2

2

1

C5P6

2

1

C5P7

2

1

C5R3

2

1

C4R3

2

1

C5R2

2

1

C4R2

2

1

C4R1

2

1

C5R4

2

1

C5R7

2

1

C5R6

2

1

C6C5

2

1

C7E7

2

1

C7D7

2

1

C7E9

2

1

C7D8

2

1

C7D6

2

1

C7E8

2

1

C6C6

2

1

C7E1

2

1

C7E5

2

1

C7E4

2

1

C7E6

2

1

C7E3

2

1

C7E2

2

1

C7D4

2

1

C7E11

2

1

C7D5

2

1

C7E10

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

X5R

1UF

0201LF
6.3V

20%

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

VCCIN

VCCIN

VCCIN

VCCIN

VCCIN

VCCIN

6.3V

0402LF

X5R

10UF

10UF
20%

20%

6.3V

X5R
0402LF

0402LF
6.3V

6.3V

10UF

220UF

3528LF

TANT

2.5V

20%

20%

220UF

3528LF

2.5V

TANT

20%

220UF

3528LF

EMPTY

2.5V

20%

220UF

3528LF

EMPTY

2.5V

EMPTY
0402LF

10UF
20%

EMPTY
0402LF

10UF
20%

EMPTY
0402LF

10UF
20%

EMPTY
0402LF

10UF
20%

EMPTY
0402LF

10UF
20%

EMPTY

10UF
20%

0402LF

6.3V

20%

0603LF

22UF

X5R

6.3V

0603LF

X5R

22UF
20%

6.3V

0603LF

22UF
20%
X5R

6.3V

22UF
20%

0603LF

X5R

X5R

20%

0603LF
6.3V

22UF

6.3V

22UF

X5R

20%

0603LF

6.3V

22UF
20%

0603LF

X5R

6.3V

22UF
20%

0603LF

X5R

COG

100PF
5%

0402LF

COG
0402LF

5%

12PF

X5R
0402LF

0.1UF
10%

6.3V

X5R

20%

10UF

0402LF

6.3V

20%

10UF

X5R
0402LF

6.3V

20%

10UF

X5R
0402LF

10UF
20%
X5R
0402LF
6.3V

0402LF
6.3V

10UF
20%
X5R

6.3V

0402LF

X5R

10UF
20%

20%

10UF

6.3V

X5R

20%

0402LF

X5R
0402LF

6.3V

X5R

20%

10UF

0402LF

X5R

20%

10UF

DECAP: VCCIN

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

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C

8

2

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3

CAD NOTE:

tiger-html.html

EMC CAPS - PLACE <5MM FROM SOC VCCIN

PACKAGE EDGE > 0402 CAPS > 0805 CAPS > BULK CAPS >POWER

COMPONENT PLACEMENT ORDER:

SECONDARY BSC

VCCIN_AUX

VCCST/VCCSTG

PRIMARY TSC

PLACE AS CLOSE AS POSSIBLE TO THE BGA

.

PRIMARY/SECONDARY SIDE

EMC CAPS

CORE PWR DECOUPLE : VCCIN_AUX/VCCST/VCCSTG

CR-24 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE24

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 24 OF 80

INTEL CONFIDENTIAL
<>

2

1

C5P12

2

1

C5P14

2

1

C5P11

2

1

C5R10

2

1

C5R9

2

1

C5P13

2

1

C6P7

2

1

C5P10

2

1

C4P8

2

1

C4P9

2

1

C6P3

2

1

C5P3

2

1

C5P4

2

1

C5N7

2

1

C5C9

2

1

C5C5

2

1

C5C4

2

1

C5P2

2

1

C6M1

2

1

C5P1

2

1

C6M2

2

1

C4N2

2

1

C4N3

2

1

C6P2

2

1

C6P1

2

1

C5P9

2

1

C5P5

2

1

C4B1

2

1

C4A4

2

1

C5B3

2

1

C4B2

2

1

C5B10

2

1

C4B5

2

1

C4B6

2

1

C4B3

2

1

C4B4

2

1

C5B2

2

1

C5B1

2

1

C5B12

2

1

C4B7

2

1

C5B11

2

1

C5B5

2

1

C5C8

2

1

C5B4

2

1

C5B7

2

1

C5C6

2

1

C4C3

2

1

C5B9

2

1

C5B8

2

1

C4C2

2

1

C5C7

2

1

C4B9

2

1

C4B8

2

1

C6C7

2

1

C6C8

2

1

C5B6

2

1

C4A5

X5R

10UF

0402LF

VCCIN_AUX

1UF
20%

6.3V

0201LF

X5R

20%

6.3V

0201LF

1UF

X5R

6.3V

0201LF

1UF
20%
X5R

1UF

6.3V

0201LF

20%
X5R

20%

6.3V

0201LF

1UF

X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

20%

1UF

6.3V

0201LF

X5R

1UF

6.3V

0201LF

20%
X5R

20%

6.3V

0201LF

1UF

X5R

10UF

0402LF

0402LF

22UF
20%
X5R
0603LF

0603LF

X5R

20%

22UF

VCCIN_AUX

0402LF

VCCIN_AUX

VCCST

VCCSTG

VCCIN_AUX

VCCIN_AUX

VCCIN_AUX

20%

2.5V

TANT

3528LF

220UF

20%
EMPTY

10UF

EMPTY
0402LF

20%

EMPTY

10UF
20%

0402LF

EMPTY
0402LF

10UF
20%

10UF

0402LF

EMPTY

20%

0402LF

10UF
20%
EMPTY

0402LF

EMPTY

10UF
20%

0402LF

20%
X5R

10UF

6.3V

X5R

6.3V

10UF
20%

0402LF

EMPTY
0402LF

10UF
20%

20%
EMPTY
0402LF

10UF

20%

6.3V

0402LF

10UF

X5R

X5R
0402LF

20%

6.3V

10UF

10UF

EMPTY
0402LF

20%

10UF
20%
X5R
0402LF
6.3V

20%
X5R

22UF

6.3V

0603LF

6.3V

6.3V

0603LF

X5R

20%

22UF

6.3V

X5R
0603LF
6.3V

22UF
20%

X5R
0603LF
6.3V

20%

22UF

6.3V

0603LF

X5R

22UF
20%

22UF
20%

0603LF
6.3V

X5R

20%

22UF

X5R

6.3V

0603LF

20%
X5R
0603LF

22UF

6.3V

0603LF
6.3V

X5R

20%

22UF

X5R

6.3V

20%

0603LF

22UF

47UF
20%
X5R
0805LF
6.3V

0805LF

20%

6.3V

47UF

20%

10UF

0402LF

EMPTY

6.3V

10UF

EMPTY
0402LF

20%

6.3V

20%

10UF

0402LF

EMPTY

6.3V

20%

10UF

0402LF

EMPTY

6.3V

20%

10UF

0402LF

EMPTY

6.3V

0402LF

EMPTY

10UF
20%

6.3V

20%

0402LF

EMPTY

6.3V

20%

10UF

0402LF

EMPTY

6.3V

20%

10UF

EMPTY
0402LF
6.3V

20%
EMPTY

10UF

6.3V

1UF

10%

X5R

10V

10%

1UF

X5R

10V

10%

10V

X5R

1UF

0402LF

10V

X5R

10%

1UF

0402LF

0402LF

5%

12PF

50V

COG

50V

5%

100PF

COG
0402LF

X5R
0402LF

10%

0.1UF

25V

DECAP : VCCIN_AUX/CCST/VCCSTG

CAD NOTE:

CAD NOTE:

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tiger-html.html

EMC CAPS

PLACE <4MM FROM SOC VDDQ, WITH EACH PAIR <12MM APART

EMC CAPS

PLACE ON THE BACK SIDE OF THE SOC

PLACE NEAR VR

VDDCDD2 PWR DECOUPLE : VDDQ_MEM

AS CLOSE AS POSSIBLE TO THE VIAS

PLACE ON THE PRIMARY SIDE,

PLACE ON THE BACK SIDE,

HAT CONNECT TO THE OUTER ROW OF SOC PINS

CR-25 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE25

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 25 OF 80

INTEL CONFIDENTIAL
<>

2

1

C5T9

2

1

C4R13

2

1

C4T6

2

1

C4T7

2

1

C4R14

2

1

C5T8

2

1

C4T5

2

1

C5T7

2

1

C5R8

2

1

C4R12

2

1

C5T1

2

1

C4R5

2

1

C5R5

2

1

C6R7

2

1

C4T2

2

1

C5T2

2

1

C4R6

2

1

C7V10

2

1

C6V1

2

1

C4T3

2

1

C5T3

2

1

C5T5

2

1

C4T4

2

1

C5T4

2

1

C5T6

2

1

C5F2

2

1

C6F3

2

1

C6F2

2

1

C5F3

2

1

C6F1

2

1

C5F1

2

1

C5F5

2

1

C5F4

2

1

C4T1

6.3V

0201LF

20%

1UF

X5R

20%

6.3V

0201LF

1UF

X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

20%

6.3V

0201LF

1UF

X5R

0201LF
6.3V

1UF
20%
X5R

6.3V

0201LF

1UF
20%
X5R

VDDQ_MEM

VDDQ_MEM

VDDQ_MEM

VDDQ_MEM

VDDQ_MEM

10V

20%

10UF

X5R
0402LF

20%

1UF

X5R
0402LF
6.3V

20%

1UF

X5R
0402LF
6.3V

20%
X5R
0402LF
6.3V

1UF

1UF
20%
X5R

6.3V

0402LF

20%

1UF

0402LF

X5R

6.3V

1UF

X5R

20%

6.3V

0402LF

X5R

20%

1UF

6.3V

0402LF

1UF

6.3V

X5R
0402LF

20%

15PF
5%

0201LF

C0G

0201LF

15PF

C0G

5%

C0G
0201LF

15PF
5%

3PF

0201LF

C0G

.25PF

3PF
.25PF

0201LF

C0G

0201LF

C0G

3PF
.25PF

47UF
20%
X5R
0603LF

20%

47UF

0603LF

X5R

10UF
20%
X5R
0402LF
10V

20%
X5R

10UF

10V

0402LF

20%
X5R
0402LF

10UF

10V

20%

10UF

0402LF

X5R

10V

10UF
20%
X5R

10V

0402LF

20%
X5R

10UF

0402LF
10V

10UF
20%
X5R

10V

0402LF

DECAP : VDD2

INTEL CORPORATION

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CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

tiger-html.html

AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED TO THE

0: PCH-LESS MODE

REVERSAL FOR ALL PEG PORTS

ARE NOT ACTIVATED)

THE CHIP WILL NOTGENERATE

PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

DISPLAY PORT PRESENCE STRAP

1:(DEFAULT)NORMAL OPERATION

PCI EXPRESS STATIC LANE

(OR RESPOND TO) SVID ACTIVITY

CFG3

CFG4

USE OF NOA ON LOCKED UNITS BUT RESERVED FOR TG

FOR ICL INTERPOSER IT IS TO ALLOW THE

RESERVED

NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT

1: DISABLED;

0: (DEFAULT)ENABLED;

EMBEDDED DISPLAY PORT

PEG DEFER TRAINING

CFG7
1: (DEFAULT) PEG TRAIN IMMEDIATELY:

0: PEG WAIT FOR BIOS FOR TRAINING

AFTER PCU PLL IS LOCKED

EAR-STALL/NOT STALL RESET SEQUENCE

1:(DEFAULT) NORMAL OPERATION
0:RESERVED

1:(DEFAULT)VRS SUPPORTING SVID PROTOCOL ARE PRESENT

SAFE MODE BOOT
CFG10

SET DFX ENABLED BIT IN DEBUG INTERFACE MSR

0 :ENABLED;

1 :(DEFAULT)DISABLED

CFG1

CFG2

CFG0

10 : DEVICE1 FUNCTION1 ENABLED DEVICE1 FUNCTION 2 DISABLED

11 : (DEFAULT)DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED

PCIE PORT BIFURCATION STRAPS

CFG[6:5]

00 : DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED

01 : DEVICE 1 FUNCTION 1 DISABLED, DEVICE 1 FUNCTION 2 ENABLED

FOLLOWING XXRESETB DE ASSERTION

CFG9

1: (DEFAULT) NORMAL
0: RESERVED

RESERVED

CFG8

0:NO VR SUPPORTING SVID IS PRESENT.

NO SVID PROTOCOL CAPABLE VR CONNECTED

0: LANE REVERSAL

1: (DEFAULT)POWER FEATURES ACTIVATED DURING RESET

0: POWER FEATURES (ESPECIALLY CLOCK GATINE

1:(DEFAULT) NORMAL OPERATION

PCH/ PCH LESS MODE SELECTION

CPU STRAPS 1

CR-26 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE26

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 26 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4P12

2

1

R4P9

2

1

R4N20

2

1

R4P1

2

1

R4P2

2

1

R4P7

2

1

R4P3

2

1

R4N19

2

1

R7D7

2

1

R7D8

2

1

R4P5

21C8

21C8

21C8

21C8

21C8

21C8

21B8

21B8

21B8

21C8

21C8

1%

1K

0402LF
1/16W

EMPTY

1%

1K

0402LF
1/16W

EMPTY

EMPTY

1/16W

0402LF

1K
1%

1/16W

1%

1K

0402LF

EMPTY

1%

1K

CH
0402LF
1/16W

0402LF

1%

1K

EMPTY

1/16W

EMPTY

1/16W

0402LF

1K
1%

1%

1K

0402LF
1/16W

EMPTY

EMPTY

1/16W

0402LF

1K
1%

EMPTY

1/16W

0402LF

1K
1%

1/16W

EMPTY
0402LF

1K
1%

STRAP : CPU STRAPS 1

CORE STRAPS 1

XDP_NOA10_N

XDP_NOA4_N

XDP_NOA9_N

XDP_NOA7_N

XDP_NOA5_N

XDP_NOA6_N

XDP_NOA2_N

XDP_NOA0_N

XDP_NOA1_N

XDP_NOA8_N

XDP_NOA3_N

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IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

tiger-html.html

RESERVED

1: (DEFAULT)NORMAL

FOR ICL INTERPOSER IT IS PM SYNC AYNC MODE

SYNCHCRONOUS (1-24 MHZ CYCLE PER BIT)

1: (DEFAULT)NORMAL

CFG11
1:(DEFULT)

DMI WILL BE CONFIGURED AS HALF SWING DC COUPLED

0: RESERVED

CFG 14

1: (DEFAULT)NORMAL

0: RESERVED

RESERVED

CFG 14

ASYNC (4-24MHZ CYCLES PER BIT)

0: RESERVED

RESERVED

CFG 12

FOR ICL INTERPOSER IT IS PM SYNC LEGACY
BUT FOR TGL IT IS RESERVED

BUT FOR TGL IT IS RESERVED

0: RESERVED;

1: (DEFAULT)NORMAL;

CFG 13

RESERVED

DMI AC COUPLING - JUST A PLACE HOLDER. NOT APPLICABLE FOR ULX-ULT

0:DMI WILL BE CONFIGURED AS FULL SWING AC COUPLED

CPU STRAPS 2

CR-27 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE27

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 27 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4P8

2

1

R4P15

2

1

R4P6

2

1

R4P13

2

1

R4P10

21C8

21C8

21C8

21C8

21C8

1%
EMPTY
0402LF
1/16W

1K

1/16W

EMPTY
0402LF

1K
1%

1%

1K

0402LF

EMPTY

1/16W

1/16W

EMPTY
0402LF

1K
1%

1/16W

EMPTY
0402LF

1K
1%

XDP_NOA12_N

XDP_NOA13_N

XDP_NOA15_N

XDP_NOA14_N

XDP_NOA11_N

STRAP : CPU STRAPS 2

CORE STRAPS 1

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

IN

IN

IN

IN

tiger-html.html

THE SPI SIGNAL TO AVOID STUB

SAMPLING - RSMRST_N

RB

RA

0:ENABLED

PLACE RA AND RB CLOSE TO

TRIPAD

BOOT HALT

1:DISABLE

0:TLS CONFD DISABLE

1:TLS CONFD ENABLE

SAMPLING - RSMRST_N

NO REBOOT

0:REBOOT ENABLED

WEAK INTERNAL PD 20KOHM

PCH STRAPS 1

NO INTERNAL PU/PD

TRIPAD

PLACE RA AND RB CLOSE TO

1:NO REBOOT

WEAK INTERNAL PD 20KOHM

0:ENABLED

RB

RA

SAMPLING - RSMRST_N

RA

RB

NO INTERNAL PU/PD

0:ENABLED

0:JTAG ODT DISABLE

1:JTAG ODT ENABLE

RB

CONSENT STRAP

1:DISABLE

NO INTERNAL PU/PD

WEAK INTERNAL PD 20KOHM

0:DISABLED

TOP SWAP OVERRIDE

1:TOP SWAP ENABLED

JTAG ODT DISABLE

THE SPI SIGNAL TO AVOID STUB

TRIPAD

1:DISABLE

A0 STRAP

SAMPLING - RSMRST_N

SAMPLING - RSMRST_N

NO INTERNAL PU/PD

SAMPLING - PCH_PWROK

TLS CONFEDENTIALLY

THE SPI SIGNAL TO AVOID STUB

PLACE RA AND RB CLOSE TO

PLACE RA AND RB CLOSE TO

SAMPLING - PCH_PWROK

RA

WEAK INTERNAL PU 20KOHM

1:DISABLE
0:ENABLED

RB

DFX TEST MODE

SAMPLING - RSMRST_N

THE SPI SIGNAL TO AVOID STUB

CR-28 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE28

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 28 OF 80

INTEL CONFIDENTIAL
<>

2

1

R4C4

2

1

R3E10

2

1

R3E8

2

1

R7R4

2

1

R7R3

2

1

R3C4

2

1

R3C5

2

1

R3C2

2

1

R3E7

2

1

R3E9

2

1

R3D6

2

1

R3D9

2

1

R3D8

2

1

R6U3

2

1

R6U1

2

1

R6T11

2

1

R6T9

22C5

10D2

64B8

10D8

37C8

11D7

10C8

10D8

37A8

11D7

10D8

37A8

1/16W

DBG_PMODE

4.7K
5%

0402LF
1/16W

EMPTY

0402LF

0402LF
1/16W

GPPC_C2_SMBALERT_N

100K

CH

1/16W

SPI0_MOSI

EMPTY

V1P8_A

GPPC_B14_SPI0_CS1

4.7K

GPPC_E6_SPI1_RST_N

SPI0_IO_2

4.7K

V3P3_A

V3P3_A

V3P3_A

V3P3_A

V1P8_S

V1P8_A

V3P3_A

V3P3_S

EMPTY

1/16W

0402LF

5%

1%

20K

1/16W

EMPTY
0402LF

EMPTY

4.7K
5%

0402LF

1%

20K

0402LF
1/16W

EMPTY

EMPTY

5%

4.7K

0402LF

EMPTY

1/16W

20K
1%

1%

4.7K

1/16W

CH

1%

100K

CH
0402LF

5%

1/16W

0402LF

EMPTY

1/16W

0402LF

1%

1/16W

0402LF

5%
EMPTY

4.7K

1/16W

0402LF

100K
1%

5%

1/16W

0402LF

EMPTY

4.7K

1/16W

0402LF

EMPTY

1%

100K

EMPTY

1/16W

0402LF

4.7K
5%

1%

100K

CH

1/16W

0402LF

GPPC_B18_SPI0_MOSI

SPI0_IO_3

STRAP : PCH STRAPS 1

CORE STRAPS 2

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

tiger-html.html

TBT LSX#2 VCCIO CONFIG

SAMPLING - RSMRST_N

WEAK INTERNAL PD 20KOHM

RA

RB

RA

SAMPLING - RSMRST_N

XTAL INPUT FREQ 1

RB

STABILIZATION DELAY

DESIGN NOTE:
PULL UP RESISTOR PRESENT ON THIS NET

10: 250MHZ

NO INTERNAL PU/PD

0:CRYSTAL ATTACHED MODE

SAMPLING - RSMRST

11: 100MHZ

NO INTERNAL PU/PD

1:SINGLE ENDED INPUT MODE

0:(DEFAULT)NO BYPASS

WEAK INTERNAL PD 20KOHM

PLACE RA AND RB CLOSE TO

THE SPI SIGNAL TO AVOID STUB

XTAL INPUT MODE

SAMPLING - DSW_PWROK

PLACE RA AND RB CLOSE TO

WEAK INTERNAL PD 20KOHM

TRIPAD

RB

RA

1:3.3V
0:1.8V

0:1.8V

01: 25MHZ

00: 24MHZ

RA

PCH STRAPS 2

RB

TRIPAD

XTAL SEL1

1:BYPASS/SKIP

XTAL INPUT FREQUENCY

1:3.3V

TBT LSX#3 VCCIO CONFIG

XTAL INPUT FREQ 0

0:(DEFAULT)CRYSTAL ATTACHED

WEAK INTERNAL PD 20KOHM

SAMPLING - RSMRST_N

THE SPI SIGNAL TO AVOID STUB

WEAK INTERNAL PD 20KOHM

1:24MHZ

THE SPI SIGNAL TO AVOID STUB

SAMPLING - RSMRST_N

RING OSCI BYPASS(HVM)

PLACE RA AND RB CLOSE TO

1:SINGLE ENDED CRYSTAL INPUT

0:(DEFAULT)38.4/19.2MHZ

SAMPLING - RSMRST_N

SKIP RTC CLK

SAMPLING - RSMRST_N

NO INTERNAL PU/PD

0:INTEGRATED CNVI ENABLE

M.2 CNVI MODES

1:INTEGRATED CNVI DISABLE(DEFAULT)

CR-29 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE29

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 29 OF 80

INTEL CONFIDENTIAL
<>

2

1

R6N3

2

1

R7P8

2

1

R7P6

2

1

R7P9

2

1

R7P7

2

1

R6P5

2

1

R6P2

2

1

R6P12

2

1

R6P3

2

1

R6P4

2

1

R6N7

2

1

R6P1

2

1

R6P10

2

1

R6P6

2

1

R6N1

2

1

R6T6

2

1

R6T3

2

1

R6P16

14C3

14B4

22C2

7B8

16C2

56D5

13B2

10C8

10C8

14B3

14B4

7B8

64A8

V3P3_A

V3P3_A

V1P8_A

V1P8_A

V3P3_A

V3P3_A

V3P3_A

V1P8_A

V3P3_A

0402LF
1/16W

20K
1%
EMPTY

EMPTY
0402LF

1%

1/16W

20K

4.7K

EMPTY
0402LF

5%

1/16W

5%

4.7K

EMPTY
0402LF
1/16W

20K

1/16W

1%
EMPTY
0402LF

EMPTY

1/16W

0402LF

1%

20K

1%

20K

0402LF
1/16W

EMPTY

1%

20K

0402LF
1/16W

EMPTY

CH

20K
1%

0402LF
1/16W

20K

0402LF
1/16W

CH

1%

1%

20K

1/16W

EMPTY
0402LF

CH

1/16W

0402LF

47K
1%

1/16W

5%

4.7K

0402LF

EMPTY

1/16W

CH
0402LF

4.7K
5%

EMPTY

20K
1%

0402LF
1/16W

EMPTY

1/16W

0402LF

4.7K
5%

CH

1/16W

0402LF

20K
1%

5%
EMPTY
0402LF

4.7K

1/16W

GPPC_F2_CNV_RGI_DT

GPPC_F10

GPPC_D12_DDP4_SDA

GPD7

STRAP : PCH STRAPS 2

CORE STRAPS 2

GPPC_E9_USB2_OC0_N

GPPC_E11_SPI1_CLK_N

GPPC_E10_SPI1_CS0_N

GPPC_F0_CNV_BRI_DT

GPPC_D10_DDP3_SDA

CAD NOTE:

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

tiger-html.html

0:1.8V

1:3.3V

1:3.3V

RB

0:1.8V

RA

MCRO LDO BYPASS

RA

SAMPLING - RSMRST_N

WEAK INTERNAL PD 20KOHM

1:LDO BYPASS
0:(DEFAULT)NO BYPASS

1:1.8V

NO INTERNAL PU/PD

0:(DEFAULT)3.3V

1:OVERRIDE

WEAK INTERNAL PD 20KOHM

0:SECUTIRY MEASURE NOT OVERRIDEN

SAMPLING - PCH_PWROK

TRIPAD

TRIPAD

FLASH DES SECUTIRY OVERRIDE

WEAK INTERNAL PD 20KOHM

RA

RB

PLACE RA AND RB CLOSE TO

RB

SAMPLING - RSMRST_N

PLACE CLOSE TO HDA SIGNAL TO AVOID STUB

WEAK INTERNAL PD 20KOHM

1:19.2MHZ FROM DIVIDER
0:38.4MHZ FROM DIRECT CRYSTAL

WEAK INTERNAL PD 20KOHM

SAMPLING - RSMRST_N

TRIPAD

SAMPLING - RSMRST_N

BOOT STRAP 2 - BIT3

BOOT STRAP 0 - BIT1

BOOT STRAP 1 - BIT2

PLACE RA AND RB CLOSE TO

TBT LSX#1 VCCIO CONFIG

PLACE RA AND RB CLOSE TO

RA

THE DDP2_SDA SIGNAL TO AVOID STUB

CPUNSSC CLK FREQ

PCH STRAPS 3

BOOT STRAP 3 - BIT4

1100: BIOS ON ESPI PERIPHERAL CHANNEL

ON ESPI ATTACHED DEVICE)

1000: SLAVE ATTACHED FLASH CONFIG (BIOS / CSME

CSME ON MASTER ATTACHED SPI

0100: BIOS ON ESPI PERIPHERAL CHANNEL

ON SPI). ESPI IS DISABLE

0010: MASTER ATTACHED FLASH CONFIG (BIOS/CSME

0000: MASTER ATTACHED FLASH CONFIG (BIOS/CSME

ON SPI). ESPI IS ENABLED (DEFAULT)

CSME ON SLAVE ATTACHED SPI

WEAK INTERNAL PD 20KOHM

SAMPLING - RSMRST_N

THE DDP1_SDA SIGNAL TO AVOID STUB

THE SML SIGNAL TO AVOID STUB

TBT LSX#0 VCCIO CONFIG

STRAP SPI 1.8V/3.3V SEL

SAMPLING - NA

BOOT STRAP/ESPI OR NON-ESPI

CR-30 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE30

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 30 OF 80

INTEL CONFIDENTIAL
<>

2

1

R3D7

2

1

R3D4

2

1

R3D3

2

1

R4F4

2

1

R4F5

2

1

R6R3

2

1

R6R1

2

1

R3E5

2

1

R3E2

2

1

R4D3

2

1

R3E6

2

1

R3E3

2

1

R4D2

2

1

R3E13

2

1

R3E12

2

1

R6U5

2

1

R6U6

2

1

R6N2

2

1

R6N5

2

1

R6U4

2

1

R3C1

2

1

R3C3

10C2

10C2

22C5

22C5

22C5

7B8

40B6

16B7

7B8

43C8

22C2

12D2

V3P3_A

GPPC_B23_SML1ALERT_N

V3P3_A

1/16W

V3P3_A

1/16W

0402LF

1%

20K

4.7K

EMPTY
0402LF
1/16W

STRAP : PCH STRAPS 3

GPPC_C5_SML0ALERT_N

1/16W

20K

1/16W

5%

0402LF

EMPTY

4.7K

V1P8_A

1%
EMPTY
0402LF

0402LF

5%

4.7K

EMPTY

V3P3_A

GPPC_H0

5%

1/16W

0402LF

1%

20K

EMPTY

GPPC_H1

EMPTY

1/16W

20K
1%

0402LF

1/16W

EMPTY

5%

4.7K

0402LF

GPPC_H2

EMPTY

1/16W

0402LF

20K
1%

EMPTY
0402LF
1/16W

5%

4.7K

V3P3_A

GPPC_E19_DDP1_SDA

0402LF

4.7K

EMPTY

1/16W

SPIVCCIOSEL

V3P3_A

V1P8_A

V3P3_A

V3P3_A

V3P3_A

V3P3_A

EMPTY

20K

CH
0402LF

4.7K
5%

1/16W

1%
EMPTY

1/16W

20K

EMPTY
0402LF
1/16W

1%

5%
CH

1/16W

4.7K

0402LF

1/16W

0402LF

5%
EMPTY

4.7K

4.7K

EMPTY
0402LF
1/16W

5%

EMPTY

1/16W

0402LF

20K
1%

2.2K 5%

0402LF CH

0402LF

4.7K
5%
EMPTY

1/16W

EMPTY

1/16W

0402LF

20K
1%

0402LF
1/16W

4.7K
5%

CH
0402LF

1%

PCH STRAPS - 1

GPPC_E21_DDP2_SDA

GPPC_F7

GPP_R2_HDA_SDO

FLASH_DES_SEC_OVERRIDE

CAD NOTE:

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

tiger-html.html

CLOSE TO SODIMM CONN

NC

NC

USE TRIPAD

DESIGN NOTE:
SPD ADDRESS FOR CHANNEL-A DIMM IS 0XA0

CR-31 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE31

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 31 OF 80

INTEL CONFIDENTIAL
<>

97
95
242
240
221
219
200
198
179
177
76
74
55
53
34
32
13
11

96
241
220
199
178
75
54
33
12

J4W1

164

255

254
253

166
260
256

108

143

161
155

134

246
245
233
232
250
249
236
237
225
224
212
211
229
228
215
216
204
203
190
191
208
207
194
195
182
183
169
170
186
187
173
174
80
79
67
66
84
83
71
70
59
58
45
46
63
62
49
50
37
38
25
24
42
41
29
28
17
16
3
4
21
20
7
8

157
149

110
109

138
140
137
139

104
100

87
88

105
101

91
92

165
162

113
115

145
150

116
114

152
156
151
158
119
120
146
121
125
122
127
126
128
131
132
133
144

J4W1

2

1

R6H1

2

1

R4J2

2

1

R4H1

R5J2

R5J1

2

1

R4H2

2

1

R4J1

2

1

C4J3

2

1

C4J2

2

1

C5H1

2

1

R6J2

2

1

R6J1

2

1

C6H5

31B7

31B7

31B7

8D3

8D3

8D3
8D3

8B3

8B3

8C3

8C3

8C3
8C3

8A3
8A1

31A5

34A5

34B7

31A5

8A3
8A3

31A7
31A7
31A7

8C3

8C3

8C3

8C3

8B8

8A3

8D8

8B3
8B3
8B3
8B3
8B3
8B3
8B3
8B3

8B3

8B3

8C3

8C3

32C2

34A7

32A5

32A5

34A7

8D8

8A3

8A3
8A3

8C8

8C8

8C8

8C8
8C8
8C8

8C8

8C8

8C8
8C8
8C8
8C8
8C8
8C8
8C8
8C8

8D8

8D8

8D8
8D8
8D8

8D8
8D8

8D8

8D8
8D8

8D8
8D8

8D8
8D8

8C8

8C8

8C8
8C8
8C8

8C8

8C8

8C8
8B8
8B8

8B8

8B8

8B8

8B8

8B8

8B8

8B8
8B8
8B8
8B8
8B8
8B8

8B8

8B8

8B8

8B8

8B8
8B8
8B8
8B8
8B8

31B7

8B2

8A1 34A5 31B7 34B7

VDDQ_MEM

VDDQ_MEM

V3P3_S

V3P3_S

V3P3_S

VDDQ_MEM

0402LF

EMPTY

16V

0.1UF
10%

CH

1/16W

1%

240

0402LF

1/16W

1%
CH

240

0402LF

10V

0.1UF
10%
X5R
0402LF

10V

0.1UF

0402LF

X5R

10%

2.2UF
20%
X5R
0402LF
6.3V

5%

0

0402LF
1/16W

CH

5%

0

0402LF
1/16W

CH

5%

0

0402LF
1/16W

CH

5%

0

0402LF

EMPTY

1/16W

5%

0

1/16W

EMPTY
0402LF

0

1/16W

0402LF

EMPTY

5%

CH

1%

240

1/16W

0402LF

H24274-001

CONN

CONN

H24274-001

SA1_DIMM0

SA0_DIMM0

SA2_DIMM0

M_0_CLK_DDR1_DN

M_0_CLK_DDR1_DP

M_0_CLK_DDR0_DP
M_0_CLK_DDR0_DN

M_0_ODT0

M_0_ODT1

M_0_CKE_0

M_0_CKE_1

M_0_CS1_N
M_0_CS0_N

M_0_PARITY
DRAM_RESET_N_R

DIMM0_TS_EVENT_N
M_0_ALERT_N
M_0_ACT_N

SA2_DIMM0
SA1_DIMM0
SA0_DIMM0

M_0_DQS_7_DN

M_0_DQS_7_DP

M_0_DQS_6_DN

M_0_DQS_6_DP

M_0_DQ_5<1>

M_0_BG0

M_0_DQ_1<6>

M_0_DQS_8_DP
M_0_DQS_8_DN
M_0_DQS_2_DP
M_0_DQS_2_DN
M_0_DQS_3_DP
M_0_DQS_3_DN
M_0_DQS_0_DP
M_0_DQS_0_DN
M_0_DQS_1_DP
M_0_DQS_1_DN

M_0_DQS_4_DN

M_0_DQS_4_DP

M_0_DQS_5_DN

M_0_DQS_5_DP

CH0_VREF_CA

SODIMM0_1_SMB_CLK_R

SODIMM0_1_SMB_DATA_R

M_0_DQ_1<1>

M_0_BG1

M_0_BA1
M_0_BA0

M_0_CB7
M_0_CB6
M_0_CB5
M_0_CB4
M_0_CB3
M_0_CB2
M_0_CB1
M_0_CB0

M_0_DQ_2<0>

M_0_DQ_2<3>

M_0_DQ_2<6>

M_0_DQ_2<5>
M_0_DQ_2<2>
M_0_DQ_2<4>

M_0_DQ_2<1>

M_0_DQ_2<7>

M_0_DQ_3<4>
M_0_DQ_3<1>
M_0_DQ_3<5>
M_0_DQ_3<3>
M_0_DQ_3<6>
M_0_DQ_3<2>
M_0_DQ_3<0>
M_0_DQ_3<7>

M_0_DQ_0<3>

M_0_DQ_0<1>

M_0_DQ_0<4>
M_0_DQ_0<6>
M_0_DQ_0<2>

M_0_DQ_0<7>
M_0_DQ_0<5>

M_0_DQ_0<0>

M_0_DQ_1<5>
M_0_DQ_1<7>

M_0_DQ_1<4>
M_0_DQ_1<0>

M_0_DQ_1<2>
M_0_DQ_1<3>

M_0_DQ_4<2>

M_0_DQ_4<0>

M_0_DQ_4<5>
M_0_DQ_4<7>
M_0_DQ_4<3>

M_0_DQ_4<6>

M_0_DQ_4<1>

M_0_DQ_4<4>
M_0_DQ_5<3>
M_0_DQ_5<2>

M_0_DQ_5<6>

M_0_DQ_5<4>

M_0_DQ_5<0>

M_0_DQ_5<7>

M_0_DQ_6<2>

M_0_DQ_5<5>

M_0_DQ_6<7>
M_0_DQ_6<4>
M_0_DQ_6<0>
M_0_DQ_6<6>
M_0_DQ_6<1>
M_0_DQ_6<5>

M_0_DQ_7<1>

M_0_DQ_6<3>

M_0_DQ_7<6>

M_0_DQ_7<5>

M_0_DQ_7<4>
M_0_DQ_7<3>
M_0_DQ_7<0>
M_0_DQ_7<2>
M_0_DQ_7<7>

DIMM0_TS_EVENT_N

1

M_0_MA<16..0>

2

0

3

4

5

6

7

9

10

8

11

12

13

14

15

16

SODIMM CH0 : CONN 1

DRAM_RESET_N_R

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

DDR4_SODIMM_2x130_RA_STD

2/4

DM8_N/DBI8_N/NC

DQS8P

DQS8N

DQS7P

DQS7N

DQS6P

DQS6N

DQS5P

DQS5N

DQS4P

DQS4N

DQS3N

DQS3P

DQS2N

DQS2P

DQS1P

DQS1N

DQS0P

DQS0N

DM6_N/DBI6_N/NC

DM7_N/DBI7_N/NC

DM4_N/DBI4_N/NC

DM5_N/DBI5_N/NC

DM3_N/DBI3_N/NC
DM2_N/DBI2_N/NC
DM1_N/DBI1_N/NC
DM0_N/DBI0_N/NC

DDR4_SODIMM_2x130_RA_STD

1/4

SA2

VREFCA

SCL

SDA

SA0

SA1

DQ37

A9
A8
A7
A6

A14/WE_N
A13
A12
A11
A10/AP

CS1_N
CS0_N

CK1P
CK1N
CK0P
CK0N

BG1
BG0

BA1
BA0

A5
A4
A3
A2
A1
A0

CKE1

RESET_N

PARITY

ODT1
ODT0

CKE0

CB7/NC
CB6/NC
CB5/NC
CB4/NC
CB3/NC
CB2/NC
CB1/NC
CB0/NC

C1/CS3_N/NC
C0/CS2_N/NC

VDDSPD

EVENT_N
ALERT_N
ACT_N

DQ63

DQ61

DQ62

DQ60
DQ59
DQ58

DQ56

DQ57

DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48

DQ46

DQ47

DQ45
DQ44
DQ43

DQ41
DQ40

DQ42

DQ39
DQ38

DQ36
DQ35
DQ34
DQ33
DQ32

DQ30

DQ31

DQ29
DQ28
DQ27

DQ25

DQ26

DQ24
DQ23
DQ22

DQ20

DQ21

DQ19
DQ18
DQ17

DQ15

DQ16

DQ14
DQ13
DQ12
DQ11
DQ10

DQ9

DQ7

DQ8

DQ5

DQ6

DQ4
DQ3
DQ2
DQ1
DQ0

A16/RAS_N
A15/CAS_N

IN

OUT

OUT

OUT

OUT

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

OUT

IN
IN
IN

IN

IN

IN

BI

BI

BI

BI
BI

BI
BI

BI

BI
BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI
BI

BI

BI

BI

BI

BI

BI
BI
BI

BI
BI

BI

BI

BI

BI

tiger-html.html

DIMM 0/1 SMBUS CONFIGURATION

RA

2: FROM PROCESSOR (DEFAULT)

1: VOLTAGE DIVIDER NETWORK (DEFAULT)

DDR VREF DIFFERENT OPTIONS (OPTION 1 AND 2 IS DEFAULT)

VREF CIRCUITRY

CH0 CA VREF FROM CPU

RB

CH0 CA VREF TO CONN

PLACE RA AND RB CLOSE TO NODE

CR-32 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE32

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 32 OF 80

INTEL CONFIDENTIAL
<>

252
251
248
247
244
243
239
238
235
234
231
230
227
226
223
222
218
217
214
213
210
209
206
205
202
201
197
196
193
192
189
188
185
184
181
180
176
175
172
171
168
167
107
106
103
102

99

98
94
93
90
89
86
85
82
81
78
77
73
72
69
68
65
64
61
60
57
56
52
51
48
47
44
43
40
39
36
35
31
30
27
26
23
22
19
18
15
14
10
9
6
5
2
1

J4W1

258

259
257

112
111
163
160
159
154
153
148
147
142
141
136
135
130
129
124
123
118
117

J4W1

2

1

R3K1

2

1

R3K2

2

1

R5H3

2

1

C5H5

2

1

R5H4

2

1

R5H1

2

1

R5H2

8A3

31B7

34A7

31A7

34A7

31A7

10A5 10D2 40C6 64B8 44A5 57A7

10A5 10D2 40C6 44A5 57A7 64B8

VDDQ_MEM

VDDQ_VTT

VDDQ_VPP

VDDQ_MEM

1/16W

1%

1K

0402LF

CH

1K
1%
CH

1/16W

0402LF

CH

5%

2

0603LF

16V

0.022UF
10%
X7R
0402LF

1/16W

CH
0402LF

24.9
1%

CH

0402LF

0 5%

CH

0402LF

0 5%

H24274-001

CONN

CONN

H24274-001

SODIMM CH0 : CONN 1

V_DDR0_VREF_CA

SODIMM0_1_SMB_DATA_R

SODIMM0_1_SMB_CLK_R

VREF_RC1

CH0_VREF_CA

SMB_SCL

SMB_SDA

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

CAD NOTE:

OUT

DDR4_SODIMM_2x130_RA_STD

4/4

VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS
VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

DDR4_SODIMM_2x130_RA_STD

3/4

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VPP
VPP

VTT

VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BI

IN

BI

BI

IN

tiger-html.html

PLACE THESE CAPS CLOSE TO SODIMM CH0

VDDQ_VPP DECAPS

PLACE THESE CAPS CLOSE TO SODIMM CH0

PLACED ON VTT PLANE CLOSE TO DIMM

PLACE 4 ON EACH SIDE OF SODIMM CH0 CLSOE TO VDD PIN

VDDQ_VTT DECAPS

VDDQ_MEM DECAPS

PLACE 4 ON EACH SIDE OF SODIMM CH0 CLSOE TO VDD PIN

CR-33 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE33

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 33 OF 80

INTEL CONFIDENTIAL
<>

2

1

C3J9

2

1

C3J3

2

1

C4J4

2

1

C3J4

2

1

C3J5

2

1

C6K2

2

1

C5H3

2

1

C6J3

2

1

C5J6

2

1

C5J2

2

1

C6J1

2

1

C6H2

2

1

C7H2

2

1

C5J4

2

1

C6K5

2

1

C6H4

2

1

C6H3

2

1

C5H2

2

1

C5K2

2

1

C5H4

2

1

C6J6

VDDQ_MEM

VDDQ_VPP

VDDQ_VTT

20%
X5R

6.3V

0603LF

10UF

20%
X5R

10UF

0603LF
6.3V

20%

1UF

X5R
0402LF
6.3V

20%

1UF

6.3V

X5R
0402LF

10UF

0603LF

X5R

20%

6.3V

0603LF

10UF
20%
X5R

6.3V

20%

10UF

6.3V

X5R
0603LF

1UF
20%

6.3V

X5R
0402LF

1UF
20%
X5R
0402LF
6.3V

20%
X5R
0402LF

1UF

6.3V

10UF

6.3V

0603LF

X5R

20%

6.3V

X5R

10UF
20%

0603LF

X5R
0603LF
6.3V

10UF
20%

6.3V

1UF
20%
X5R
0402LF

X5R

6.3V

1UF
20%

0402LF

20%

1UF

6.3V

0402LF

X5R

6.3V

X5R

20%

1UF

0402LF

X5R

6.3V

1UF
20%

0402LF

X5R
0402LF

1UF
20%

6.3V

6.3V

20%

10UF

X5R
0603LF

0603LF

20%

10UF

X5R

6.3V

SODIMM CH0 : PWR DECAP

CAD NOTE:

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

tiger-html.html

SPD ADDRESS FOR CHANNEL-B DIMM IS 0XA4

USE TRIPAD

NC

NC

CLOSE TO SODIMM CONN

CR-34 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE34

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 34 OF 80

INTEL CONFIDENTIAL
<>

2

1

C5J5

2

1

C4K4

2

1

C4J5

164

255

254
253

166
260
256

108

143

161
155

134

246
245
233
232
250
249
236
237
225
224
212
211
229
228
215
216
204
203
190
191
208
207
194
195
182
183
169
170
186
187
173
174
80
79
67
66
84
83
71
70
59
58
45
46
63
62
49
50
37
38
25
24
42
41
29
28
17
16
3
4
21
20
7
8

157
149

110
109

138
140
137
139

104
100

87
88

105
101

91
92

165
162

113
115

145
150

116
114

152
156
151
158
119
120
146
121
125
122
127
126
128
131
132
133
144

J4Y1

2

1

R4K3

R4K1

2

1

R6J3

2

1

R6K2

2

1

R6K1

97
95
242
240
221
219
200
198
179
177
76
74
55
53
34
32
13
11

96
241
220
199
178
75
54
33
12

J4Y1

2

1

R6J4

2

1

C6J7

R5J4

R4K4

2

1

R4K2

R5J3

31A7

32A5

32A5

31B7

34A6

8A1

31A5

34A5

31B7

9B8

9B8

9B8

34B7

9B8

9C3

9C3

9C3

9D8

35C2

9B8

9B8

9B8

9B8

9B8

9B8
9B8

9B2

9B8

9C8

9C8

9C8

9C8

9C8

9C8

9C8

9B8
9C8

9B8

9B8

9C8

9C8

9C8

9C8

9C8

9C8

9C8
9C8

9C8

9C8

9C8

9C8

9A3

9A3

34A5

9C3

9B3

9B3

9A3

9C3

9A3

9A3

9A3

9A3

9D3

9D3

9D3

9D3

9C3

9C3

34A6

34A6

9B8

9B8

9B8

9B8

9B8

9B8

9B8

9B8

9B8

9D8

9D8

9D8
9D8

9D8

9D8

9D8

9D8

9D8

9D8

9D8

9D8

9D8

9C8
9C8

9C3

9C3

9B3

9B3

9C3

9B3

9B3

9B3

9B3

9B3

9B3

9B3

9B3

9C8

9D8

9C8
9D8

34B7

34B7

34B7

8A1 31A5 31B7 34B7

V3P3_S

VDDQ_MEM

VDDQ_MEM

VDDQ_MEM

V3P3_S

VDDQ_MEM

V3P3_S

EMPTY
0402LF
1/16W

0
5%

0
5%
CH
0402LF
1/16W

5%
EMPTY
0402LF
1/16W

0

5%

0

0402LF
1/16W

CH

EMPTY

16V

0.1UF
10%

0402LF

0402LF

CH

1%

240

1/16W

H24275-001

CONN

CH

1/16W

0402LF

240
1%

1%

0402LF

CH

1/16W

240

0402LF

CH

0

1/16W

5%

5%

0

0402LF
1/16W

EMPTY

0
0

1/20W

0402LF

CH

H24275-001

CONN

10%
X5R
0402LF
10V

0.1UF

6.3V

0402LF

X5R

20%

2.2UF

10V

0.1UF

0402LF

X5R

10%

SODIMM0_1_SMB_CLK_R

SODIMM0_1_SMB_DATA_R

SA0_DIMM1

DRAM_RESET_N_R

M_1_CB1

M_1_DQ_6<4>

M_1_DQ_6<2>

M_1_DQ_6<7>

DIMM1_VDDQMEM

DIMM1_TS_EVENT_N

M_1_DQ_6<6>

M_1_DQS_7_DN

M_1_DQS_7_DP

M_1_DQS_6_DN

M_1_CB3

M_1_CB4

M_1_DQ_1<1>

SODIMM CH1 : CONN2

CH1_VREF_CA

M_1_DQ_5<7>

M_1_DQ_5<1>

M_1_DQ_5<0>

M_1_DQ_5<6>

M_1_DQ_5<4>

M_1_DQ_5<3>
M_1_DQ_5<5>

M_1_CB5

2

0

1

3

4

5

6

7

9

10

8

11

12

13

14

15

M_1_MA<16..0>

16

M_1_DQ_5<2>

M_1_DQ_4<2>

M_1_DQ_4<4>

M_1_DQ_4<0>

M_1_DQ_4<5>

M_1_DQ_4<3>

M_1_DQ_4<1>

M_1_DQ_4<6>

M_1_DQ_7<2>
M_1_DQ_4<7>

M_1_DQ_7<6>

M_1_DQ_7<4>

M_1_DQ_3<5>

M_1_DQ_3<1>

M_1_DQ_3<3>

M_1_DQ_3<7>

M_1_DQ_3<4>

M_1_DQ_3<0>

M_1_DQ_2<1>
M_1_DQ_2<5>

M_1_DQ_2<0>

M_1_DQ_2<4>

M_1_DQ_2<3>

M_1_DQ_2<6>

M_1_ACT_N

M_1_ALERT_N

DIMM1_TS_EVENT_N

M_1_CB0

M_1_CB2

M_1_CB6

M_1_CB7

M_1_CKE_0

M_1_ODT0

M_1_ODT1

M_1_PARITY

M_1_CKE_1

M_1_BA0

M_1_BA1

M_1_BG0

M_1_BG1

M_1_CLK_DDR0_DN

M_1_CLK_DDR0_DP

M_1_CLK_DDR1_DN

M_1_CLK_DDR1_DP

M_1_CS0_N

M_1_CS1_N

SA1_DIMM1

SA2_DIMM1

M_1_DQ_7<1>

M_1_DQ_7<5>

M_1_DQ_7<3>

M_1_DQ_7<7>

M_1_DQ_7<0>

M_1_DQ_6<1>

M_1_DQ_6<3>

M_1_DQ_6<5>

M_1_DQ_6<0>

M_1_DQ_1<0>

M_1_DQ_1<6>

M_1_DQ_1<7>
M_1_DQ_1<4>

M_1_DQ_1<5>

M_1_DQ_1<3>

M_1_DQ_0<7>

M_1_DQ_0<6>

M_1_DQ_0<2>

M_1_DQ_0<3>

M_1_DQ_0<0>

M_1_DQ_0<5>

M_1_DQ_0<1>

M_1_DQ_2<2>
M_1_DQ_2<7>

M_1_DQS_5_DN

M_1_DQS_5_DP

M_1_DQS_4_DN

M_1_DQS_4_DP

M_1_DQS_6_DP

M_1_DQS_1_DN

M_1_DQS_1_DP

M_1_DQS_0_DN

M_1_DQS_0_DP

M_1_DQS_3_DN

M_1_DQS_3_DP

M_1_DQS_2_DN

M_1_DQS_2_DP

M_1_DQS_8_DN

M_1_DQS_8_DP

M_1_DQ_3<2>

M_1_DQ_1<2>

M_1_DQ_3<6>
M_1_DQ_0<4>

SA0_DIMM1

SA2_DIMM1

SA1_DIMM1

DRAM_RESET_N_R

DESIGN NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT

DDR4_SODIMM_2x130_RA_STD

2/4

DM8_N/DBI8_N/NC

DQS8P

DQS8N

DQS7P

DQS7N

DQS6P

DQS6N

DQS5P

DQS5N

DQS4P

DQS4N

DQS3N

DQS3P

DQS2N

DQS2P

DQS1P

DQS1N

DQS0P

DQS0N

DM6_N/DBI6_N/NC

DM7_N/DBI7_N/NC

DM4_N/DBI4_N/NC

DM5_N/DBI5_N/NC

DM3_N/DBI3_N/NC
DM2_N/DBI2_N/NC
DM1_N/DBI1_N/NC
DM0_N/DBI0_N/NC

OUT

BI

OUT

OUT

DDR4_SODIMM_2x130_RA_STD

1/4

SA2

VREFCA

SCL

SDA

SA0

SA1

DQ37

A9
A8
A7
A6

A14/WE_N
A13
A12
A11
A10/AP

CS1_N
CS0_N

CK1P
CK1N
CK0P
CK0N

BG1
BG0

BA1
BA0

A5
A4
A3
A2
A1
A0

CKE1

RESET_N

PARITY

ODT1
ODT0

CKE0

CB7/NC
CB6/NC
CB5/NC
CB4/NC
CB3/NC
CB2/NC
CB1/NC
CB0/NC

C1/CS3_N/NC
C0/CS2_N/NC

VDDSPD

EVENT_N
ALERT_N
ACT_N

DQ63

DQ61

DQ62

DQ60
DQ59
DQ58

DQ56

DQ57

DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48

DQ46

DQ47

DQ45
DQ44
DQ43

DQ41
DQ40

DQ42

DQ39
DQ38

DQ36
DQ35
DQ34
DQ33
DQ32

DQ30

DQ31

DQ29
DQ28
DQ27

DQ25

DQ26

DQ24
DQ23
DQ22

DQ20

DQ21

DQ19
DQ18
DQ17

DQ15

DQ16

DQ14
DQ13
DQ12
DQ11
DQ10

DQ9

DQ7

DQ8

DQ5

DQ6

DQ4
DQ3
DQ2
DQ1
DQ0

A16/RAS_N
A15/CAS_N

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI
BI

BI
BI

BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

IN

BI

IN

IN

IN

IN

IN

IN

IN
IN
IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN
IN

OUT

tiger-html.html

DDR VREF DIFFERENT OPTIONS (OPTION 1 AND 2 IS DEFAULT)
1: VOLTAGE DIVIDER NETWORK (DEFAULT)
2: FROM PROCESSOR (DEFAULT)

CH1 CA VREF TO CONN

CH1 CA VREF FROM CPU

RA

PLACE RA AND RB CLOSE TO NODE

RB

VREF CIRCUITRY

CR-35 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE35

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 35 OF 80

INTEL CONFIDENTIAL
<>

252
251
248
247
244
243
239
238
235
234
231
230
227
226
223
222
218
217
214
213
210
209
206
205
202
201
197
196
193
192
189
188
185
184
181
180
176
175
172
171
168
167
107
106
103
102

99

98
94
93
90
89
86
85
82
81
78
77
73
72
69
68
65
64
61
60
57
56
52
51
48
47
44
43
40
39
36
35
31
30
27
26
23
22
19
18
15
14
10
9
6
5
2
1

J4Y1

258

259
257

112
111
163
160
159
154
153
148
147
142
141
136
135
130
129
124
123
118
117

J4Y1

2

1

R5J6

2

1

R5J5

2

1

R5K1

2

1

C5K1

2

1

R5K2

9A3

34A7

VDDQ_MEM

VDDQ_VTT

VDDQ_VPP

VDDQ_MEM

CH

1/16W

1%

24.9

0402LF

X7R

10%

0.022UF

0402LF
16V

2 5%

0603LF CH

CH

1%

1K

0402LF
1/16W

1/16W

CH
0402LF

1K
1%

CONN

H24275-001

H24275-001

CONN

VREF_RC2

V_DDR1_VREF_CA

CH1_VREF_CA

SODIMM CH1 : CONN 2

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

DESIGN NOTE:

IN

DDR4_SODIMM_2x130_RA_STD

4/4

VSS

VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS
VSS

VSS
VSS

VSS

VSS

VSS

VSS
VSS

VSS

VSS
VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

DDR4_SODIMM_2x130_RA_STD

3/4

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VPP
VPP

VTT

VDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

OUT

tiger-html.html

VDDQ_VPP DECAPS

VDDQ_VTT DECAPS

PLACE THESE CAPS CLOSE TO SODIMM CH0

VDDQ_MEM DECAPS

PLACEHOLDER

PLACED ON VTT PLANE CLOSE TO DIMM

PLACE THESE CAPS CLOSE TO SODIMM CH0

PLACE 4 ON EACH SIDE OF SODIMM CH0 CLSOE TO VDD PIN

PLACE 4 ON EACH SIDE OF SODIMM CH0 CLSOE TO VDD PIN

CR-36 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE36

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 36 OF 80

INTEL CONFIDENTIAL
<>

2

1

C6K1

2

1

C4H1

2

1

C6H1

2

1

C4K3

2

1

C4K1

2

1

C3J7

2

1

C3J6

2

1

C3J8

2

1

C5K3

2

1

C6K3

2

1

C4K2

2

1

C5K4

2

1

C6K4

2

1

C7H1

2

1

C6J4

2

1

C5J1

2

1

C4J1

2

1

C6J5

2

1

C5J3

2

1

C4H2

2

1

C5J7

2

1

C6J2

VDDQ_MEM

VDDQ_MEM

VDDQ_VPP

VDDQ_VTT

0603LF

20%

10UF

X5R

6.3V

0603LF

10UF
20%

6.3V

X5R

X5R

1UF
20%

0402LF
6.3V

0402LF

1UF

X5R

20%

6.3V

0603LF

X5R

10UF
20%

6.3V

20%

10UF

X5R
0603LF
6.3V

0603LF

10UF

X5R

20%

6.3V

0402LF

20%

1UF

6.3V

X5R

20%

1UF

X5R
0402LF
6.3V

10UF
20%
X5R
0603LF
6.3V

10UF
20%
X5R
0603LF
6.3V

10UF
20%
X5R
0603LF
6.3V

0402LF

X5R

20%

1UF

6.3V

20%

1UF

X5R

6.3V

0402LF

6.3V

0603LF

X5R

10UF
20%

6.3V

1UF

X5R
0402LF

20%

0402LF

20%
X5R

6.3V

1UF

X5R

20%

1UF

0402LF
6.3V

20%

10UF

X5R
0603LF
6.3V

20%
X5R

6.3V

0402LF

1UF

20%

1UF

X5R
0402LF
6.3V

7343LF

6.3V

EMPTY

330UF

20%

SODIMM CH1 : PWR DECAP

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

tiger-html.html

RA

56 OHM FOR 3.3V

RA RESISTOR SHOULD BE
33 OHM FOR 1.8V

FET SWITCH FOR ISOLATION

CR-37 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE37

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 37 OF 80

INTEL CONFIDENTIAL
<>

2

1

R2G12

2

1

R2H1

2

1

R2G20

2

1

R2G13

2

1

R2G15

2

1

R8U7

2

1

R2G19

2

1

R2G16

2

1

R2G18

2

1

R2G17

2

1

R8U3

2

1

R8U8

2

1

R8U9

2

1

R8U10

2

1

R2G14

EP

14

13

12

11

10

9

8

7

6

5

4

3

2

1

U2G1

2

1

C8U1

EP

14

13

12

11

10

9

8

7

6

5

4

3

2

1

U8U1

2

1

C2G1

37C5

37C4

39B2

38C4

39B5

39B5

38C4

38C7

37C5

38C4

37D4

37C4

38A7

38A5

38C4

38A1

37C7

10D8

10D8

28B5

37B5

39B5

38A7 38C7

37A5

10D8

28B2

10C8

10D8

10C8
10D8

28C2

38A1

37A8

37A5

37A5

38A5

37C5

38A7

V3P3_A_SPI_CON

V5_A

V5_A

V3P3_A_SPI_CON

0402LF

10UF

X5R

6.3V

20%

IC
E72154-001

X5R

10UF
20%

0402LF
6.3V

IC
E72154-001

100K

0402LF CH

5%

CH

1K
5%

1/16W

0402LF

5%

56

0402LF CH

CH
0402LF

5%

1K

1/16W

5%

0

EMPTY

0402LF

5%

56

0402LF CH

5%

56

0402LF CH

5%

56

0402LF CH

5%

56

0402LF CH

5%

56

0402LF CH

56 5%

CH

0402LF

5%

56

0402LF CH

5%

0

CH

0402LF

0 5%

CH

0402LF

5%

0

0402LF CH

SPI0_MISO_SW

SPI0_CLK_SW

SPI0_MOSI_TPM

SPI0_HOLD_N

SPI0_CLK_TPM

SPI0_MISO_TPM

SPI0_MISO_R

SPI0_CLK_R

SPI0_MOSI_SW

SPI0_WP_N

SPI0_MISO_SW

SPI0_MOSI_SW

SPI0_DQ2_HDR

SPI0_MOSI_HDR

SPI0_MOSI_R

PCH_SPI_OE_N

SPI : FLASH FET SWITCH

SPI : FLASH FET SWITCH

SPI0_MISO

SPI0_MOSI

SPI0_DQ2_SW

SPI0_TPM_SW_CS_N

SPI0_CS0_R_N

SPI0_DQ3_SW

SPI0_IO_3
SPI0_CS0_N

SPI0_CLK

SPI0_TPM_CS_N
SPI0_IO_2

PCH_SPI_OE_N

SPI0_DQ2_SW

SPI0_DQ3_SW

SPI0_CLK_HDR

SPI0_CLK_SW

SPI0_MISO_HDR

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN
IN

SN74CBT3125RGYR

EP

4A

2A

1A

3A

2B

GND

1B

4B

VCC

4OE_N

3OE_N

2OE_N

1OE_N

3B

SN74CBT3125RGYR

EP

4A

2A

1A

3A

2B

GND

1B

4B

VCC

4OE_N

3OE_N

2OE_N

1OE_N

3B

OUT

IN

OUT

IN

IN

IN

OUT

IN

tiger-html.html

32MB SPI FLASH

SPI PROG HEADER

SPI FLASH/ PROG HEADER

CR-38 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE38

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 38 OF 80

INTEL CONFIDENTIAL
<>

2

1

R7V4

2

1

3

Q8V1

2

1

3

Q7U1

8

9

7
3
2
5

4

6

1

EU2G1

2

1

R3H3

2

1

R7U2

2

1

C7U2

2

1

R8V2

2

1

C8U3

2

1

R8V3

8

7

6

5

4

3

2

1

J8V1

2

1

C8U2

37A5

38A7

37C2

37A2

37A8 37C7

79B1

16C7

79B8

38A5

37D2

37B2

37C2

37C2
37C2
38A4

37D2

37A5

38C7

37B2

V3P3_A_SPI_CON

V5_A

V3P3_A_SPI_CON

V3P3_A

V3P3_A

V3P3_A_SPI_CON

V3P3_A

0402LF

X5R

10%

0.1UF

10V

K32927-001

MHDR

1/16W

0402LF

CH

1%

20K

6.3V

0402LF

10UF
20%
X5R

1/16W

CH

5%

100K

0402LF

0.22UF
10%
X5R
0402LF
10V

EMPTY

0402LF

5%

1K

CH

0402LF

0 0

W25R256JVEIQ

J69420-001

IC

C81974-001

MOSFET

C81974-001 MOSFET

1/16W

CH

5%

100K

0402LF

V5A_SPI_R

SPI0_CS0_R_N

SPI0_CLK_R

SPI0_HOLD_N

SPI : FLASH & HDR

SPI : FLASH

DEDIPROG_IO3_RSMRST_N

PCH_SPI_OE_N

RSMRST_N

DEDIPROG_IO3

SPI0_MISO_R

SPI0_WP_N

SPI0_MOSI_R

SPI0_CLK_HDR
SPI0_MOSI_HDR

DEDIPROG_IO3

SPI0_MISO_HDR

SPI0_CS0_R_N

SPI0_DQ2_HDR

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

IN

IN

OUT

IN

IN

D

S

G

D

S

G

_CS

THPAD

IO3

CLK

IO0

IO2
IO1

VCC

GND

BI

IN

IN

OUT

BI
BI
BI

2x4MHDR_PG

8

7

6

5

4

3

2

1

BI
BI

tiger-html.html

PLACE CLOSE TO
DEVICE VDD/GND PINS

SPI TPM CHIP

SLB9670XQ2.0

CR-39 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE39

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 39 OF 80

INTEL CONFIDENTIAL
<>

2

1

R8V1

2

1

C9U5

2

1

R8U11

2

1

C8V1

2

1

R9V2

2

1

R9V1

2

1

C8V2

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

EU8V1

10C7

37D2

37C2

37B2

37A5

16A1

64B3

79B5

40C5

47A4

48A4

50C7

52A8

57A7

60A8

63A7

V3P3_A

V3P3_A

V3P3_A

IC

K71205-001

0.1UF
10%
X7R

16V

0402LF

5%

1/16W

0402LF

EMPTY

0

5%

0

1/16W

0402LF

CH

X5R

10%

1UF

0402LF

10V

5%

CH

0402LF

0

X7R

16V

0.1UF
10%

0402LF

CH

1/16W

0402LF

100K
5%

GPPC_E13_TPM_IRQ

SPI0_MISO_TPM

SPI0_CLK_TPM

SPI0_MOSI_TPM

SPI0_TPM_SW_CS_N

PM_PLTRST_N

TPM_RST_N

SPI_PP

SPI : TPM 2.0

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

IN

OUT

IN

IN

OUT

slb9670

EP

GND

NCI

NC

NC

NCI

NCI

NCI

NCI

MISO

GND

VDD

MOSI

CS#

SCLK

PIRQ#

RST#

NCI/GND

NCI

NCI/VDD

NCI

NCI

NCI

NCI

GND

VDD

PP

GPIO

NCI

NCI

NCI

GND

NCI/VDD

tiger-html.html

INTERNAL PD AT 150KOHM

INTERNAL PU AT 150KOHM

500MA

HDMI_1 : HDMI ACTIVE LVL SHIFTER

INTERNAL PD AT 150KOHM

CR-40 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE40

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 40 OF 80

INTEL CONFIDENTIAL
<>

2

1

R8D1

2

1

R8C1

2

1

C3P4

2

1

R3P2

2

1

R3N10

2

1

R2N17

2

1

R2N21

2

1

R2N13

2

1

R2N10

2

1

C7C5

2

1

C7D3

2

1

C7D2

2

1

C7C4

2

1

C3N3

2

1

C3N2

2

1

C7D1

2

1

C3N4

2

1

C7C7

2

1

R2P3

2

1

R3P4

2

1

C3P2

2

1

C7C3

2

1

C7C6

18

15

46
43

24

1

6

26

10

35

37

4

25

9

11

30

2

33

8

34

7

36

27

23

22

20

19

17

16

14

13

38
39

41
42

44
45

47
48

31

40

21

32

49

5

3

28
29

12

U3N2

2

1

C8D13

2

1

C8D15

2

1

R8D8

2

1

C8D14

7

6

5

4

3

2

1

U8D1

2

1

R3P3

2

1

R3N7

2

1

R3N8

3

1

CR3N2

3

1

CR3N1

2

1

R3P1

2

1

R3P5

2

1

R3N9

2

1

C3P1

2

1

C3P7

2

1

C3P8

2

1

C3P5

2

1

C3P6

2

1

C3P3

2

1

R8C4

2

1

R3P6

40B6

41B8
41B8

40C8

40B2

40C6

40C5

40C5

16C7

79A7

77A8

40B8

7B8

30B8

7B8

40C8

7D2

7D2

40B2 41A3 41C2

40B2 41A3 41C2

10A5

10D2

32A2

44A5

57A7

64B8

40B2

7D2

7D2

41D8

41D8

41C8

40C8

7D2

7D2

16A1

64B3

79B5

39B7

47A4

48A4

50C7

52A8

57A7

60A8

63A7

10A5

10D2

32A2

64B8

44A5

57A7

40C8

7D2
7D2

40B6

40A4 41A3 41C2

7B8

40A4 41A3 41C2

40A1

41A8

41A8

41C8

41A3 41C2

40C8

V3P3_S

V3P3_S

V3P3_S

V3P3_S

V5_S

V3P3_S

V3P3_S

V1P2_HDMI

V1P2_HDMI

V3P3_S

5%

1/16W

0402LF

EMPTY

4.7K

0 5%

CH

0402LF

X5R

10%

0.1UF

0402LF

1/16W

0402LF

5%

4.7K

EMPTY

0

CH

0

0402LF

1/16W

4.7K
5%
EMPTY
0402LF

30V

DIO

100MA

C83455-001

30V
100MA
DIO

C83455-001

2.2K
5%

1/16W

0402LF

CH

5%

2.2K

0402LF
1/16W

CH

0402LF

5%

1/16W

EMPTY

4.7K

IC

K68901-001

10V

0402LF

20%

1UF

X5R

CH

0 5%

0402LF

1UF

X5R

20%

0402LF
10V

10UF
20%

0402LF

X5R

6.3V

K30000-001

IC

10V

0402LF

X5R

10%

0.1UF

10%

0.1UF

X5R

10V

0402LF

4.99K

1/16W

CH
0402LF

1%

CH

0402LF

0 5%

10V

10%

0.1UF

0402LF

X5R

10V

0.1UF

0402LF

10%
X5R

10V

0.1UF
10%

0402LF

X5R

50V

10%

0.01UF

0402LF

X7R

10%
X7R

50V

0402LF

0.01UF

10%

0.01UF

0402LF

X7R

50V

50V

X7R
0402LF

0.01UF
10%

0402LF

20%

10V

X5R

4.7UF

10%
X5R
0402LF

0.1UF

10V

0402LF

5%

0

CH
0402LF

5%

0

CH

EMPTY

4.7K
5%

0402LF
1/16W

5%

4.7K

EMPTY

1/16W

0402LF

5%

4.7K

EMPTY
0402LF
1/16W

4.7K

0402LF

EMPTY

5%

1/16W

5%

2.2K

0402LF
1/16W

CH

2.2K

0402LF

CH

1/16W

5%

HDMI1_EQ

HDMI1_DATA0_DN
HDMI1_DATA0_DP

HDMI_I2C_ADDR

HDMI_RESET_N

HDMI1_PRE

HDMI1_DCIN_EN

HDMI_I2C_ADDR

HDMI_ID

PM_SLP_S0_N

HDMI1_REXT

GPPC_E19_DDP1_SDA
GPPC_E18_DDP1_SCL

HDMI1_EQ

DDI1_HDMI_CLK_DN

DDI1_HDMI_DATA2_DP

DDI1_HDMI_DP0

HDMI1_SCL

HDMI1_SDA

SMB_SDA

HDMI : HDMI ALS

HDMI1_PD_N

DDI1_HDMI_DATA2_DN

DDP1_SDA_R

DDI1_HDMI_CLK_DP

DDI1_HDMI_DP1

DDI1_HDMI_DN0

DDI1_HDMI_DP2

HDMI1_DATA2_DP

HDMI1_DATA2_DN

HDMI1_DATA1_DP

HDMI_ID

DDI1_HDMI_DATA1_DN

DDI1_HDMI_DATA1_DP

PM_PLTRST_N

SMB_SCL

HDMI1_DCIN_EN

DDI1_HDMI_DATA0_DP
DDI1_HDMI_DATA0_DN

HDMI_V1P2_EN

HDMI1_REXT

HDMI1_C_SCL

HDMI1_C_SDA

HDMI1_SCL

DDI1_HDMI_DN2

HDMI_SMB_SCL

HDMI_SMB_SDA

DDI1_HDMI_DN1

DDSP_HPD1

HDMI1_SDA

HDMI1_PD_N

HDMI1_CLK_DP

HDMI1_CLK_DN

HDMI1_DATA1_DN

DDI1_HDMI_CLKP
DDI1_HDMI_CLKN

HDMI1_HPD

HDMI1_PRE

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

DESIGN NOTE:

DESIGN NOTE:

OUT

OUT

OUT

IN

IN

BI
BI

IN

IN

PS8409AQFN48ITR2_A2

GND_TPD

IN_CLK-

IN_CLK+

VDDRX12_46

IN_D0-

IN_D0+

VDDRX12

IN_D1-

IN_D1+

HPD_SRC

IN_D2-

IN_D2+

PWRSWITCH

REXT

RESET_N

SCL_SRC_AUXP

SDA_SRC_AUXN

HDMI_ID

I2C_ADDR

VDD12

CSCL

CSDA

PRE

RSV2

NC_25

VDD33_24

OUT_D2+

OUT_D2-

HPD_SNK

OUT_D1+

OUT_D1-

VDDTX12_18

OUT_D0+

OUT_D0-

VDDTX12

OUT_CLK+

OUT_CLK-

CEC_EN

VDDA12

RSV1

HDMI_CEC

SDA_SNK

SCL_SNK

VDD12_6

EQ

PD_N

DCIN_ENB

TESTMODEB

VDD33

TPS7A1112PDRVR

THERMAL PAD

IN

GND

BIAS

EN

NC

OUT

BI

BI

OUT

IN

BI

OUT

OUT

OUT

IN

OUT

OUT
OUT

OUT
OUT

BI

BI

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN

IN

OUT

BI

BI

OUT
OUT

tiger-html.html

PLACE ESD CLOSE TO CONN

THICK TRACE FOR POWER PIN

HDMI : HDMI CMC/ESD & STD CONN

CR-41 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE41

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 41 OF 80

INTEL CONFIDENTIAL
<>

2

1

C7A2

2

1

R3N6

10

9

7

6

8

3

5

4

2

1

U3N1

10

9

7

6

8

3

5

4

2

1

U7B1

10

9

7

6

8

3

5

4

2

1

U7A1

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

J3L1

2

1

C7C1

2

1

F7B1

1

2

CR7B1

2

1

C7C2

2

1

R3N1

2

1

R3N2

2

1

R7A2

2

1

R7A1

2

1

R3N3

2

1

R3N4

2

1

R7A4

2

1

R7A3

4

2

3

1

L3N1

4

2

3

1

L7A1

4

2

3

1

L3N2

4

2

3

1

L7A2

40B2

40B2

40A4

40B2

41C2

41B3 41D3

40A4

40B2

41C2

41B3 41D3

40B2

40A4

40B2

41A3

40B2

40B2

40B2

41B3 41D3

41A3 41D5

40B2

41B3 41D3

40B2

41B3 41D5

41B3 41D5

41B3 41D5

40A4

40B2

41A3

41A3

40B2

40B2

41C2

41B6

41D3

41B6

41D3

41A5

41D5

41A5

41D5

41C6

41D5

41D6

41D3

41D6

41D3

41C6

41D5

41C6

41B3

41C6

41B3

41A5

41B3

41A5

41A3

41D6

41B3

41D6

41B3

41B6

41B3

41B6

41B3

V5_HDMI1

V5_S

150MA

20%

CHIP

90OHM

150MA

20%

CHIP

90OHM

CHIP

90OHM

20% 150MA

20% 150MA

CHIP

90OHM

EMPTY

0201LF

5%

0

5%

0

0201LF EMPTY

EMPTY

5%

0201LF

0

EMPTY

0201LF

0 5%

EMPTY

5%

0201LF

0

5%

EMPTY

0

0201LF

EMPTY

5%

0

0201LF

5%

0201LF

0

EMPTY

X5R

10%

0.1UF

0402LF
10V

1A

DIO

20V

FUSE

1.1A

10V

X5R

10UF

0402LF

20%

CONN
H17597-001

IC
H89865-001

IC

IC

100K

0402LF
1/16W

CH

5%

0402LF

EMPTY

5%

3.3PF

HDMI1_DATA0_DP

HDMI1_DATA0_DN

HDMI1_SCL

HDMI1_DATA2_C_DP

HDMI1_SDA

HDMI1_DATA0_C_DN

HDMI1_DATA1_DP

HDMI1_SCL

HDMI1_DATA2_DP

HDMI1_DATA2_DN

HDMI1_CLK_DP

HDMI1_DATA2_C_DN

HDMI : HDMI CMC/ESD & CONN

HDMI1_CLK_C_DN

HDMI1_DATA1_DN

HDMI1_DATA0_C_DP

HDMI1_CLK_DN

HDMI1_DATA1_C_DN

HDMI1_DATA1_C_DP

HDMI1_CLK_C_DP

V5S_HDMI

HDMI1_SDA

HDMI1_HPD

HDMI1_HPD

HDMI1_DATA0_C_DP

HDMI1_DATA0_C_DN
HDMI1_CLK_C_DP

HDMI1_CLK_C_DN

HDMI1_DATA1_C_DP

HDMI1_DATA2_C_DP

HDMI1_DATA2_C_DN

HDMI1_DATA1_C_DN

HDMI1_DATA1_C_DP

HDMI1_DATA1_C_DN

HDMI1_CLK_C_DP

HDMI1_CLK_C_DN

HDMI1_DATA2_C_DP

HDMI1_DATA2_C_DN

HDMI1_DATA0_C_DN

HDMI1_DATA0_C_DP

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

BI

BI

OUT

IN

IN

IN

IN

OUT

IN

IN

IN

IN

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

RCPT_HDMI_19P_4MTG_VT

IO19

IO18

IO17

IO16

IO15

IO14

IO13

IO12

IO11

IO10

IO2

IO3

IO4

IO5

IO6

IO7

IO8

IO9

IO1

MH1

MH2

MH3

MH4

IN

IN

IN

tiger-html.html

PLACE ESD CLOSE TO CONN

DP++ : DP CMC/ESD

CR-42 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE42

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 42 OF 80

INTEL CONFIDENTIAL
<>

10

9

7

6

8

3

5

4

2

1

U6B1

10

9

7

6

8

3

5

4

2

1

U4M1

10

9

7

6

8

3

5

4

2

1

U6A1

2

1

C6A2

2

1

C6A1

2

1

R6A1

4

3

2

1

L6A1

2

1

R6A2

2

1

C4M4

2

1

C4M3

2

1

R4M7

4

3

2

1

L4M2

2

1

R4M6

2

1

R6A4

4

3

2

1

L6A2

2

1

R6A3

2

1

C6A4

2

1

C6A3

2

1

C4M2

2

1

C4M1

2

1

R4M4

4

3

2

1

L4M1

2

1

R4M5

42A3 43B3

42A3 43B3

42A5

43B3

42D5

43B3

42D5

43B3

42B5

43B3

42B5

43B3

42A5

43B3

42C5

43B3

42C5

43B3

42B3 43B3

42A3 43B3

42C3 43B3

42B3 43B3

42B3 43B3

7C2

7C2

7C2

7C2

7C2

7C2

7C2

7C2

42A3 43B3

43A3

43D4

43B3

43B8

43A3

43A4

43A3

43D1

0201LF

0

EMPTY

5%

90OHM

100MA

J16541-001

CHOKE

NA

5%

EMPTY

0

0201LF

10%

0.1UF

0402LF X5R

0.1UF

0402LF

10%

X5R

10%

0.1UF

0402LF X5R

X5R

0402LF

0.1UF 10%

0201LF

5%

EMPTY

0

CHOKE

J16541-001

NA

100MA

90OHM

EMPTY

0201LF

0 5%

0201LF EMPTY

0 5%

CHOKE

J16541-001

NA

100MA

90OHM

EMPTY

0201LF

5%

0

0402LF

0.1UF 10%

X5R

10%

0.1UF

0402LF X5R

EMPTY

5%

0

0201LF

J16541-001

NA

100MA

90OHM
CHOKE

0201LF

0

EMPTY

5%

X5R

0402LF

0.1UF 10%

10%

0.1UF

0402LF X5R

H89865-001

IC

H89865-001

IC

IC
H89865-001

DP_LANE2_DP

DP_LANE2_DN

DP_LANE3_DP

DP_LANE0_DN

DP_LANE0_DP

DP_LANE2_DN

DP_LANE2_DP

DP_LANE3_DN

DP_LANE1_DN

DP_LANE1_DP

DP_LANE3_DN

DP++ : CMC/ESD

DP_LANE0_DN

DP_LANE1_DP

DP_LANE1_DN

DP_LANE3_DP

DDI2_DP_LANE0_DN

DDI2_DP_LANE1_DP

DDI2_DP_LANE1_DN

DDI2_DP_LANE2_DP

DDI2_DP_LANE2_DN

DDI2_DP_LANE3_DP

DDI2_DP_LANE3_DN

DDI2_DP_LANE0_C_DN

DDI2_DP_LANE0_C_DP

DDI2_DP_LANE1_C_DN

DDI2_DP_LANE1_C_DP

DDI2_DP_LANE2_C_DP

DDI2_DP_LANE3_C_DN

DDI2_DP_LANE3_C_DP

DDI2_DP_LANE0_DP

DDI2_DP_LANE2_C_DN

DP_LANE0_DP

DP_SDA_AUX_DN

DP_OB_AUX_EN

DP_HPD

DP_SCL_AUX_DP

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

IN

IN

tiger-html.html

CA; EDGE RATE CONTROL CAP

CA

DP++ DUAL MODE SUPPORT PROTECTION CIRCUIT

CA

QA

QA-REVERSED SOURCE-DRAIN ON ISOLATION GATE PASS

HIGH :HDMI DONGLE

LOW : DP

DP_OB_AUX_EN

DP++ : DP STD CONN

CR-43 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE43

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 43 OF 80

INTEL CONFIDENTIAL
<>

1

2

6

Q6B2

4

5

3

Q6B2

2

1

C6C2

2

1

C6C1

2

1

R4M3

2

1

R6B1

2

1

R6B2

1

2

6

Q4M1

4

5

3

Q4M1

2

1

3

Q6A1

2

1

3

Q5M1

1

2

6

Q6B1

4

5

3

Q6B1

2

1

R4M2

2

1

R4N1

2

1

C6A7

2

1

C6A5

2

1

C6A6

2

1

F6A1

2

1

R6A5

2

1

R4M1

2

1

C6C4

2

1

R6C1

2

1

R6B3

2

1

R6B4

2

1

C6C3

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

J4M1

7B8

42B5

42A3

42A5

42B3

43D4

42D4

42C4

43A4

43D1

42D4

42C4

43B8

42A5

42B3

42B5

42A3

42C5

42B3

42D5

42A3

42C5

42C3

42D5

42A3

43A3 42C4

43C4
43C7

43A3 42D4

7B8

43B6

43C7

43B5

43C6

43B3

42C4

43A3 42D4

7C2

43C3 43C6

7B8

30B5

7C2

43B5

43C3

43B6

43C4

V5_S

V5_S

V5_S

V3P3_S

V3P3_S

V3P3_S

V3P3_S

V5_S

G62474-001

CONN

10%

X5R

0402LF

0.1UF

0402LF

5%

CH

0

2.2K

0402LF
1/16W

CH

5%

1/16W

5%

0402LF

CH

2.2K

0.1UF

0402LF

10%

X5R

0402LF

CH

5%

100K

1/16W

5%

1M

0402LF
1/16W

CH

FUSE

1.1A

X5R

6.3V

0402LF

20%

22UF

20%

22UF

6.3V

0402LF

X5R

X5R

10%

0.1UF

0402LF
10V

0402LF

100K
1%
CH

1/16W

0402LF
1/16W

1%

100K

CH

MOSFET

BSS138DW

D52888-001

MOSFET

BSS138DW

D52888-001

MOSFET

C81974-001

D45305-001 MOSFET

MOSFET

D52888-001

BSS138DW

BSS138DW

MOSFET

D52888-001

CH

1%

0402LF
1/16W

100K

CH

100K
1%

1/16W

0402LF

0201LF

1M
5%

1/20W

CH

5%
C0G

100PF

0201LF

C0G

100PF
5%

0201LF

MOSFET

BSS138DW

MOSFET

BSS138DW

DP++ : STD CONN

DDSP_HPD2

V3P3S_DP_PWR

DP_LANE2_DN

DP_LANE3_DN

DP_CONFIG_2

DP_SDA_AUX_DN
DP_HPD

DP_SCL_AUX_DP

DP_OB_AUX_EN

DP_LANE3_DP

DP_LANE2_DP

DP_LANE1_DN

DP_LANE0_DN
DP_LANE1_DP

DP_LANE0_DP

DP_HPD

V3P3S_DP

DP_AUX_EN

DP_SCL_AUX_DP

GPPC_E20_DDP2_SCL

DP_AUX_EN

DP_DDC_EN

DP_OB_AUX_EN

DP_SDA_AUX_DN

DDI2_DP_AUX_DP

DDI2_DP_AUX_C_DP

DP_DDC_EN

GPPC_E21_DDP2_SDA

DDI2_DP_AUX_DN

DDI2_SDA

DDI2_DP_AUX_C_DN

DP_DDC_EN

DP_AUX_EN

DESIGN NOTE:

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

IN

IN

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

IN

FET_N_DUAL

D

S

G

FET_N_DUAL

D

S

G

IN

FET_N_DUAL

G

S

D

FET_N_DUAL

G

S

D

D

S

G

D

S

G

FET_N_DUAL

G

S

D

FET_N_DUAL

G

S

D

OUT

OUT

IN

CONN_DISPLAYPORT_20P_4MTG_RA

MH4

MH3

MH2

MH1

IO20

IO11

IO14

IO16

IO17

IO18

IO15

IO13

IO12

IO19

IO10

IO2

IO5

IO7

IO8

IO6

IO3

IO4

IO9

IO1

tiger-html.html

TRIPAD

CFG[4:1] FOR CONFIGURATION

TO CH7511B

LVDS : DDI SIGNALS

NC

NC

FROM CPU

CR-44 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE44

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 44 OF 80

INTEL CONFIDENTIAL
<>

2

1

R9J1

EP

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30
29

28

27

26

25

24

23
22
21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2
1

U9J1

2

1

C1W6

2

1

C1W7

2

1

C1W9

2

1

C1W8

2

1

C1W1

2

1

C1W4

2

1

C1W5

2

1

C1W2

2

1

C1W3

2

1

C9H14

2

1

R9H4

2

1

R9H7

2

1

R9K2

2

1

R9K1

2

1

R9J2

2

1

R1W2

2

1

R1W1

2

1

R9J8

2

1

R9J6

2

1

R9J4

2

1

R9J7

2

1

R9J5

2

1

R9J3

2

1

R9H2

2

1

R9H1

2

1

R9H6

2

1

R9H5

2

1

C9H6

2

1

C9H5

2

1

C9H9

2

1

C9H10

2

1

C9H1

2

1

C9H2

45B8
45B4

44B5

45C3

45C5

45C3

45C5

45C3

44C5

11C1

10A5

10D2

32A2

40C6

57A7

64B8

10A5

10D2

32A2

40C6

64B8

57A7

44C5
44B5

44D5
44D5

44C5

44A8
44A8
44A8
44A8

45C3
45C5

45C3
45C5

45C5

45C3

45C5

45C3

45C5

45C3

45C5

45C3

45C5

45C3

45C5

45C3

7D8

7D8

7D8

44B4

44C4

44B4

44B4

44B4

7D8

7D8

7C8

44C4

7C8

44B4

44B4

44B4

44B4

44A1

V1P8_A_LVDS

V3P3_S

V3P3_S

V3P3_S

V3P3_S

0402LF

0.1UF

X7R

10%

16V

0402LF

0.1UF 10%

X7R

16V

0402LF

0.1UF

X7R

10%

16V

0402LF

0.1UF

X7R

16V

10%

16V

0402LF X7R

0.1UF 10%

0402LF

10%

16V

X7R

0.1UF

1%

100K

CH
0402LF
1/16W

5%

0

CH

0402LF

1/16W

0402LF

EMPTY

100K
1%

100K

1/16W

0402LF

1%
EMPTY

1%

10K

0402LF
1/16W

EMPTY

1%

10K

0402LF
1/16W

EMPTY

1%

10K

0402LF
1/16W

EMPTY

1%

10K

0402LF
1/16W

CH

1%

10K

0402LF
1/16W

EMPTY

1%

10K

0402LF
1/16W

EMPTY

1%

10K

0402LF
1/16W

EMPTY

1%

10K

0402LF
1/16W

EMPTY

0402LF
1/16W

10K

CH

5%

0402LF CH

5%

0

0402LF CH

5%

0

0402LF

0 5%

CH

1/16W

0402LF

5%

10K

CH

0402LF

20%

X5R

1UF

4.7UF

X5R
0402LF

20%

6.3V

20%
X5R
0402LF
10V

1UF

10V

0.1UF
10%
X5R
0402LF

0402LF

10%
X5R

10V

0.1UF

10%

0.1UF

10V

X5R
0402LF

0.1UF

10V

X5R
0402LF

10%

10%

0402LF

X5R

10V

0.1UF

0402LF

20%

4.7UF

X5R

6.3V

10V

X5R
0402LF

0.1UF
10%

IC

10K

1/16W

0402LF

EMPTY

5%

LVDS_PWM
LVDS_ENAVDD

LVDS_HPD

LVDS_ENABKL

LVDSB_DATA3_N

LVDSB_DATA3_P

LVDSB_DATA2_N

LVDSB_DATA2_P

EDP_D1_DN

GPPC_D18_LVDS_IRQ

SMB_SDA

LVDS_MS_SDA
LVDS_MS_SCL

SMB_SCL

LVDS_MODE_SEL

LVDS_PD_N

LVDS_EPS_N

LVDS_RST_N

EDP_AUX_C_DP
EDP_AUX_C_DN

EDP_D0_DP
EDP_D0_DN

EDP_D1_DP

LVDS_CFG4
LVDS_CFG3
LVDS_CFG2
LVDS_CFG1

LVDSB_DATA0_P
LVDSB_DATA0_N

LVDSB_DATA1_P
LVDSB_DATA1_N

LVDSA_DATA3_N

LVDSA_DATA3_P

LVDSA_CLK_CE_N

LVDSA_CLK_CE_P

LVDSA_DATA2_N

LVDSA_DATA2_P

LVDSA_DATA1_N

LVDSA_DATA1_P

LVDSA_DATA0_N

LVDSA_DATA0_P

LVDSB_CLK_CE_N

LVDSB_CLK_CE_P

DDIA_TX0_DP

DDIA_TX0_DN

DDIA_TX1_DP

LVDS_CFG3

EDP_AUX_C_DP

LVDS : DDI SIGNALS

LVDS_CFG4

LVDS_CFG2

LVDS_CFG1

DDIA_TX1_DN

DDIA_AUX_DP

DDIA_AUX_DN

EDP_AUX_C_DN

DDPA_HPD

EDP_D0_DP

EDP_D0_DN

EDP_D1_DP

EDP_D1_DN

LVDS_HPD

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

BI

IN

IN

OUT

OUT

OUT

OUT

PTN3460BS/F6

PD_N

DEV_CFG

TESTMODE
EPS_N

MS_SCL

MS_SDA

DDC_SCL

DDC_SDA

BKLTEN

CFG4
CFG3
CFG2
CFG1

PVCCEN

PWMO

NC

NC

NC

RST_N

LVSDO_N

LVSDO_P

LVSCKO_N

LVSCKO_P

LVSCO_N

LVSCO_P

LVSBO_N

LVSBO_P

LVSAO_N

LVSAO_P

LVSDE_N

LVSDE_P

LVSCKE_N

LVSCKE_P

LVSCE_N

LVSCE_P

LVSBE_N

LVSBE_P

LVSAE_N

LVSAE_P

HPDRX

GNDREG

GNDREG

GND

EP

DP1_P
DP1_N

DP0_N

DP0_P

VDD(3V3)

VDD(3V3)

VDD(3V3)

VDD(1V8)

VDD(3V3)

VDD(1V8)

VDD(1V8)

AUX_P
AUX_N

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

IN
IN

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

IN

IN
IN

IN
IN
IN
IN

IN

BI

OUT

OUT
OUT
OUT
OUT

OUT

IN

IN

BI

BI

BI

IN

tiger-html.html

BACKLIGHT CONTROL

VDD_LVDS POWER GENERATION

4A

LVDS : POWER & CONN

12V BACKLIGHT GENERATION

CR-45 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE45

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 45 OF 80

INTEL CONFIDENTIAL
<>

2

1

R8K2

2

1

R8K1

4

5

3

Q8K1

1

2

6

Q8K1

2

1

R8K3

2

1

R8K5

2

1

R8K4

2

1

C9H8

2

1

R9H8

2

1

C9H7

1

5

2

8

3

7

U9H1

2

1

C9H13

2

1

R9H3

2

1

R1Y1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

J1Y1

2

1

C1Y2

2

1

C1Y1

45B5

44C1

44B1

44B1

44C1

45C3

44B1

7A8

44B1

60A3

60B3

44B1

44B1

44C1

44B1

44C1

44B1
44B1
44B1

44C1
44C1

44C1
44C1

44C1

44C1

44C1
44C1

44C1

V3P3_S

V3P3_S

V12_S

VDD_BKL

V3P3_S

V3P3_S

VDD_BKL

VDD_LVDS

VDD_LVDS

10UF

25V

0805LF

10%
X5R

X5R

10%

0.1UF

25V

0402LF

H49300-001

HDR

0
1A

0603LF
200V

CH

0

CH

5%

0402LF

10UF

X5R

10V

20%

0402LF

K36991-001

IC

0.1UF

X5R
0402LF

10%

25V

0

0603LF CH

1A

X7R

10%

0402LF
50V

2200PF

EMPTY

5%

0

0402LF

5%

0

0402LF CH

EMPTY

0402LF

0 5%

BSS138DW

MOSFET

BSS138DW

MOSFET

5%

4.7K

CH
0402LF
1/16W

CH
0402LF

1K
1%

1/16W

LVDS_BKLCTRL

LVDSB_CLK_CE_N

LVDSB_DATA2_P

LVDSB_DATA1_P

LVDSB_DATA0_P

LVDS_BKLCTRL

LVDS_BKLCTRL_PWM

LVDS_PWM

LVDS_BKLCTRL_EN

DDIA_BKLTCTL

LVDS_ENABKL

SIO_BKLCTL

LVDSB_DATA0_N

LVDS_ENAVDD

LVDSB_CLK_CE_P

LVDSB_DATA3_P

LVDS_ENAVDD_R

LVDSA_CLK_CE_P

LVDS_ENAVDD_OUT

LVDS_ENAVDD_C

LVDSB_DATA1_N
LVDSB_DATA2_N
LVDSB_DATA3_N

LVDSA_DATA0_P
LVDSA_DATA1_P

LVDSA_DATA2_N
LVDSA_DATA3_N

LVDSA_DATA0_N

LVDSA_CLK_CE_N

LVDSA_DATA2_P
LVDSA_DATA3_P

LVDSA_DATA1_N

LVDS : PWR & HDR

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

G

FET_N_DUAL

D

S

G

FET_N_DUAL

D

S

IN

IN

IN

SLG5NT1502VTR

S

D

ON

VDD

GND

CAP

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

2X15HDR

tiger-html.html

M.2 KEY E : SLOT

RA PLACE 12.7MM - 25.4MM FROM CONNECTOR

PLACE RB CLOSE TO CONNECTOR

RA

PCIE GEN 2

NUT IPN:

NUT MPN:

K66505-001

F40M20-301126BS-1

RB

VENDOR_DEFINED

RA

TP FOR CLK DEBUG PURPOSE

CR-46 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE46

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 46 OF 80

INTEL CONFIDENTIAL
<>

1

TP3E1

2

1

R8R7

2

1

R7R10

2

4

3

1

L8U1

2

1

R8U2

2

1

R8U1

2

1

R3F7

1

TP2E2

1

TP2E1

MTG77

MTG76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

J7T1

2

1

R7R11

2

1

R7R18

2

1

C3F1

2

1

C3F2

2

1

R8R5

2

1

R7R9

2

1

R8R4

2

1

R3F3

2

1

R3F6

2

1

C3F4

2

1

C7T1

2

1

C7T2

2

1

C8R7

2

1

C8R8

2

1

C8R9

2

1

C3F3

47A1

47C2

47B2

14B2

47B5

47A5

47C5

12A6

12A6

12A6

12A6

47B5

14B2

47C5

47C5

14C3

15C7

14C3

22C5

14B3

13D2

13D2

15C2

13B7

13C7

13C7

11D1

50C8

57A3

16C2

46B7

14C3

14C3

14C3

14C3

14C3

14C3

14C3

13B7

15C7

14C3

46A5

15C2

14C3

14C3

14C3

V3P3_A_WLAN

V3P3_A_WLAN

V3P3_A

V3P3_A_WLAN

V3P3_A_WLAN

0.01UF
10%

0402LF
50V

X7R

X5R

20%

10UF

0402LF
10V

0.1UF

X7R

16V

10%

0402LF

50V

X7R

0.01UF
10%

0402LF

10%

0402LF

0.1UF

X5R

10%

0.1UF

X5R

0402LF

X7R

10%

50V

0402LF

0.01UF

0402LF

5%

CH

0

1%

200K

CH

1/16W

0402LF

0402LF

5%

1/16W

CH

10K

5%

33

0402LF CH

CH

5%

0

0201LF

0402LF

X7R

0.1UF
10%

16V

10UF
20%
X5R
0402LF

50 1%

CH

0402LF

0402LF CH

1%

50

K65309-001

CONN

REV=1

TP

TP

EMPTY

0402LF

0

0

0201LF

5%

EMPTY

0

5%

0

EMPTY

0201LF

IND

752402-015

90OHM

CH

1%

100K

1/16W

0402LF

CH

0603LF

0 1A

WLAN_RST_N

BT_KILL_N

WIFI_KILL_N

KEYE_DEBUG

KEYE_SUSCLK

KEYE_CNV_RGI_DT

PCIE3_P6_TX_C_DN

PCIE3_P6_TX_C_DP

DISC_WLAN_WWAN_COEX2

DISC_WLAN_WWAN_COEX1

KEYE_CLINK_CLK

KEYE_UART_WAKE_N

KEYE_LED1_N

KEYE_BT_PCMFRM_CRF_RST_N

KEYE_LED2_N

KEYE_BT_PCMOUT_CLKREQ

KEYE_BT_PCMIN

KEYE_BT_PCMCLK

DISC_WLAN_WWAN_COEX3

KEYE_CNV_RGI_RSP

KEYE_CNV_BRI_DT

KEYE_CLINK_DATA

KEYE_CLINK_RST_N

CNV_WR_CLK_DP

PCIE3_P1_CLK_DN

GPPC_F3_CNV_RGI_RSP

GPPC_H19

GPPC_F1_CNV_BRI_RSP

USB2_P10_DP

USB2_P10_C_DN

USB2_P10_C_DP

USB2_P10_DN

SUS_CLK

KEYE_CNV_BRI_RSP

PCIE3_P6_RX_DP

PCIE3_P6_TX_DN

PCIE3_P6_TX_DP

M.2 KEY E : SLOT

GPPC_D13_KEYE_WAKE

PM_WAKE_N

WLAN_PEWAKE0_N

CNV_WT_D0_DN

CNV_WT_D0_DP

CNV_WT_CLK_DN

CNV_WT_CLK_DP

CNV_WT_D1_DP

CNV_WR_D0_DN

CNV_WR_CLK_DN

PCIE3_P6_RX_DN

PCIE3_P1_CLK_DP

CNV_WT_D1_DN

WLAN_PEWAKE0_N

CLK_P1_REQ_N

CNV_WR_D1_DP

CNV_WR_D0_DP

CNV_WR_D1_DN

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

CAD NOTE:

CHOKE_4P

IN

IN

OUT

T_POINT1

T_POINT1

KEY E

NGFF_E_PLTFRM

SLOT A KEY E

KEY E

KEY E

PS

CS

PINS_REV_0.90

UIM_PWR_SRC/GPIO1/PEWAKE1_N

UIM_PWR_SNK/CLKREQ1_N

UIM_SWP/PERST1_N

GND_75

CLKREQ0*

PEWAKE0*

GND_57

GND_63

RESERVED_2ND_PETP1

REFCLKP0

PERP0

PERN0

PETN0

GND_39

PETP0

GND_33

SDIO_RESET*

SDIO_WAKE*

SDIO_DATA3

SDIO_DATA2

SDIO_DATA1

SDIO_DATA0

SDIO_CMD

GND_7

SDIO_CLK

USB_D-

USB_D+

ALERT

RESERVED_64

I2C_CLK

PERST0*

RESERVED_W_DISABLE2*

SSCLK

COEX1

COEX2

RESERVED_42

UART_TX

UART_RX

I2C_DATA

PCM_IN/I2S_SD_IN

PCM_OUT/I2S_SD_OUT

3.3V_72

3.3V_74

GND_45

REFCLKN0

GND_51

RESERVED_2ND_PETN1

RESERVED/REFCLKP1

RESERVED/REFCLKN1

GND_69

RESERVED_2ND_PERN1

RESERVED_2ND_PERP1

W_DISABLE1*

GND_1

COEX3

RESERVED_40

RESERVED_38

UART_RTS

UART_CTS

PCM_SYNC/I2S_WS

PCM_CLK/I2S_SCK

LED1*

3.3V_2

3.3V_4

UART_WAKE*

GND_18

LED2*

MTG77

MTG76

IN

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

tiger-html.html

TO MCP

CLINK

WIFI_KILL_N

BT_KILL_N

M.2 KEY E : CLINK, RF_KILL

KEYE_CLINK

WLAN RESET

KEYE/B_COEX

CR-47 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE47

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 47 OF 80

INTEL CONFIDENTIAL
<>

2

1

R3E18

2

1

R3E17

2

1

R3E16

2

1

R7R17

2

1

R7R15

2

1

R7R16

2

1

C7R3

4

5

3

2

1

U7R2

2

1

R3E1

2

1

R7R14

2

1

R7R13

2

1

R7R12

2

1

R3F5

2

1

R3F4

2

1

R3F2

2

1

R3F1

46B2

12C1

46B2

46B2

10B8

12C1

46B2

46B1

14B3

46B2

48B3

10B8

46B2

46B2

11B7

48B3

48B3

46B2

11B7

10B8

11D1

16A1

64B3

79B5

39B7

40C5

48A4

50C7

52A8

57A7

60A8

63A7

V3P3_A_WLAN

V3P3_A_WLAN

V3P3_S

V3P3_S

0402LF
1/16W

10K

EMPTY

5%

10K

EMPTY

5%

1/16W

0402LF

CH

0

0402LF

0

0402LF

0

0

CH

0201LF CH

0 5%

0201LF CH

5%

0

0201LF CH

0 5%

1/16W

0402LF

CH

10K
5%

C78568-001

IC

0.1UF

0402LF

10%
X5R

10V

CH

0201LF

0 5%

CH

0 5%

0201LF

0201LF

0

CH

5%

0201LF CH

5%

0

0201LF

5%

0

CH

0201LF CH

0 5%

M.2 KEY E : CLINK, RF_KILL

WIFI_KILL_N

GPPC_A11

KEYE_CLINK_DATA

KEYE_CLINK_RST_N

CNV_WLAN_CLINK_RST_N

GPPC_A13_KEYE_BTKILL

BT_KILL_N

WLAN_RST_N

CNV_PA_BLANKING

DISC_WLAN_WWAN_COEX3

WLAN_WWAN_COEX1

CNV_WLAN_CLINK_CLK

KEYE_CLINK_CLK

DISC_WLAN_WWAN_COEX2

CNV_MFUART2_TXD

WLAN_WWAN_COEX3

WLAN_WWAN_COEX2

DISC_WLAN_WWAN_COEX1

CNV_MFUART2_RXD

CNV_WLAN_CLINK_DATA

GPPC_D14_KEYE_RST

PM_PLTRST_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

BI

OUT

OUT

IN

OUT

BI

G

74AHC1G08

V

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

BI

IN

OUT

OUT

IN

IN

IN

tiger-html.html

STUFF 0OHM IF WISH TO USE SEPARATE RST FOR WWAN RESET

PLACE CLOSE TO PIN CONN

WWAN RESET

M.2 KEY B : SLOT (WWAN/SSD)

K66505-001

NUT IPN:

F40M20-301126BS-1

NUT MPN:

PLACE CLOSE TO PIN CONN

CR-48 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE48

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 48 OF 80

INTEL CONFIDENTIAL
<>

2

1

R8J1

2

1

R8H4

2

1

R8F1

2

4

3

1

L9G1

2

1

R9G11

2

1

R9G12

2

1

C8G6

2

1

C8G4

2

1

C8G3

2

1

C2V1

2

1

R8H3

2

1

C8H1

4

5

3

2

1

U8H1

2

1

R8H2

2

1

R8H1

2

1

C2W1

2

1

C2V2

2

1

R2V3

2

1

R2U11

2

1

R2U7

2

1

R2W4

2

1

R2V1

2

1

R2U8

2

1

R2W3

2

1

R2U13

2

1

R2U14

2

1

R1V1

2

1

R2V5

2

1

C9H12

2

1

C9H11

8

7
9

75

30

36

34

32

68

66

67

55

53

54

37

49

35

47

50

31

43

29

41

69

58

56

MH1

23

26

10

28

24

22

20

48

46

44

42

40

73

71

57

51

45

39

33

27

11

5

3

6

25

38

21

60
62
64

1

52

65

63

61

59

74

72

70

4

2

J8H1

2

1

R2U10

2

1

R2U12

2

1

C8G5

2

1

R2V4

2

1

C2W2

2

1

C9H4

2

1

C9H3

2

1

R2V2

2

1

R2W2

2

1

R2W1

11D7

16A1

64B3

79B5

39B7

40C5

47A4

50C7

52A8

57A7

60A8

63A7

48C2

48B6
48D6

13B7
13B7

48A6

15C7

48A6

13C1

15C7

13D7
13D7

13B7

48A1

49B8

12B6

12B6

49C8

48A6

48A6

48C3

11C1

11D1

15C2

11D1

11C1

13B7

13C2

12B6

13C1 48B6

48D3

48C6

13D7

13C2

13D7

48A4

48A4

12B6

49B8

47A8

47B8

47B8

V3P3_A_KEYB

UIM_PWR

V3P3_S

V3P3_S

V3P3_A_KEYB

V3P3_A_KEYB

V3P3_A_KEYB

V3P3_A_KEYB

V3P3_A_KEYB

V1P8_A

V3P3_A

V1P8_A

1/16W

0402LF

1%
EMPTY

10K

10K
1%
CH

1/16W

0402LF

1/16W

0402LF

EMPTY

10K
1%

10%

0.22UF

X5R

0402LF

0.22UF
0402LF

10%

X5R

0.01UF

50V

0402LF

X7R

10%

1%

100K

CH

1/16W

0402LF

0402LF

0.01UF
10%
X7R

50V

0402LF

0 5%

CH

0402LF CH

5%

0

KIT

(NUT: QTY=1)

NGFF_B_2280_CARD

K70884-001

0402LF X5R

10%

0.22UF

0.22UF
0402LF X5R

10%

0402LF

1/16W

CH

1%

10K

0201LF

5%

0

CH

EMPTY

1%

0402LF
1/16W

10K

1/16W

EMPTY
0402LF

1%

10K

10K

1/16W

1%
EMPTY
0402LF

10K
1%

1/16W

EMPTY
0402LF

10K

1/16W

1%

0402LF

EMPTY

1/16W

1%
EMPTY
0402LF

10K

1/16W

0402LF

1%
EMPTY

10K

1%

100K

CH
0402LF
1/16W

CH

0

0201LF

5%

X7R

10%

16V

0.1UF

0402LF

50V

COG

33PF
5%

0402LF

10K

EMPTY
0402LF
1/16W

1%

0402LF

CH

10K
5%

1/16W

C78568-001

IC

0.1UF

X5R

10%

0402LF

10V

0201LF

EMPTY

5%

0

6.3V

100UF

X5R
1206LF

20%

6.3V

100UF
20%

1206LF

X5R

X7R
0402LF
16V

0.1UF
10%

0402LF
50V

5%
COG

33PF

EMPTY

5%

0

0201LF

0201LF EMPTY

0 5%

752402-015

90OHM

IND

0

0805LF CH

1A

5%

0

0201LF CH

5%

CH

0201LF

0

GPPC_B17_SPI0_MISO

PM_PLTRST_N

GPPC_B17_WWAN_RST_N

KEYB_WWAN_PERST_N

KEYB_WWAN_CONFIG2
KEYB_WWAN_CONFIG3

PCIE3_P5_RX_DN
PCIE3_P5_RX_DP

KEYB_WWAN_CONFIG2

PCIE3_P2_CLK_DP

KEYB_WWAN_RST_N
KEYB_WWAN_CONFIG1

PCIE3_P2_CLK_DN

PCIE3_P12_RX_DN
PCIE3_P12_RX_DP

SIM_GPIO_0

PCIE3_P12_TX_C_DN
PCIE3_P12_TX_C_DP

PCIE3_P5_TX_DN

KEYB_WWAN_PEWAKE_N

KEYB_WWAN_PERST_N

UIM_IO

KEYB_I2S1_RXD
KEYB_GNSS_DISABLE
KEYB_I2S1_SFRM
UIM_RST_N

PCIE3_P5_TX_C_DN

KEYB_WWAN_CONFIG0

KEYB_WWAN_CONFIG3

KEYB_WWAN_DISABLE_N

GPPC_D1_KEYB_FCP_OFF

GPPC_D16_KEYB_WAKE_N

CLK_P2_REQ_N

GPPC_D15_KEYB_DISABLE_N

GPPC_D0_KEYB_RST

PCIE3_P5_TX_DP

USB2_P6_DP

KEYB_I2S1_SCLK

KEYB_WWAN_CONFIG1

KEYB_WWAN_FCP_OFF_N

M.2 KEY B : SLOT

KEYB_WWAN_CONFIG0

PCIE3_P12_TX_DN

USB2_P6_DN

PCIE3_P12_TX_DP

KEYB_USB_DP
KEYB_USB_DN

PCIE3_P5_TX_C_DP

KEYB_WWAN_FCP_OFF_N
KEYB_WWAN_DISABLE_N

KEYB_I2S1_TXD

UIM_CLK

SIM_DET

WLAN_WWAN_COEX1

WLAN_WWAN_COEX2

WLAN_WWAN_COEX3

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

CHOKE_4P

IN

IN

OUT

G

74AHC1G08

V

IN

OUT

IN

OUT

IN

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

PS

CS

PLATFORM PIN OUT

KEY B

NGFF_B_CONN_KIT

MH1

3P3V_74

3P3V_72

3P3V_70

SSCLK

SIM_DETECT

COEX1

COEX2

COEX3

NC_58

NC_56

PEWAKE_N

CLKREQ_N

PERST_N

GPIO_4

GPIO_3

GPIO_2

GPIO_1

GPIO_0

DEVSLP

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

GPIO_8

GPIO_10

GPIO_7

GPIO_6

GPIO_5

GPIO_9/DAS/DSS_N

W_DISABLE_N

FULL_CARD_POWER_OFF_N

3P3V_4

3P3V_2

USB3.0IND/GND-OTHER

GND_73

GND_71

PEDET_OC-PCIE/GND-SATA

RESET_N

ANTCTL3

ANTCTL2

ANTCTL1

ANTCTL0

GND_57

REFCLKP

REFCLKN

GND_51

PETP0/SATA-A+

PETN0/SATA-A-

GND_45

PERP0/SATA-B-

PERN0/SATA-B+

GND_39

PETP1/USB3.0-TX+

PETN1/USB3.0-TX-

GND_33

PERP1/USB3.0-RX+

PERN1/USB3.0-RX-

GND_27

DPR

GPIO_11

CONFIG_0

GND_11

USB_D-

USB_D+

GND_5

GND_3

COBFIG_3

IN
IN

IN

BI

OUT
OUT

OUT

OUT

IN

OUT

IN

IN

IN
IN

IN

IN

OUT
OUT

BI

BI

IN

IN

OUT
OUT
OUT
OUT

tiger-html.html

M.2 KEY B : SINGLE NANO SIM SLOT

CR-49 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE49

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 49 OF 80

INTEL CONFIDENTIAL
<>

2

1

C1V1

S6

S5

S4

S3

S2

S1

G4

G3

G2

G1

J1U1

C2

A3

A2

B2

C3

C1

B3

B1

U9G2

48C2

48C2

48C2

49B4

49B4

49C4

49C5

49B5

49B5

E88783-001

IC

K67510-001

CONN

0.1UF
10%

10V

0402LF

X5R

UIM_PWR

UIM_PWR

UIM_CLK

UIM_IO

UIM_RST_N

UIM_ESD_RST_N

UIM_ESD_CLK

UIM_ESD_IO

M.2 KEY B : NANO SIM SLOT

UIM_ESD_RST_N

UIM_ESD_CLK

UIM_ESD_IO

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CONN_NANO_SIMCARD_6P

GND

GND

GND

GND

I/0

VPP (PROGRAM V)

GND

CLK (CLOCK)

RST (RESET)

VCC (SUPPLY V)

IN

IN

BI

OUT

OUT

BI

IN

VCC

RST_IN

CLK_IN

DATA_IN

RST_EXT

CLK_EXT

DATA_EXT

GND

IN

BI

intel.com

tiger-html.html

LAN1_0P9V_CTRL AND V0P9_A_LAN

PLACE CLOSE TO DEVICE I225

16MBIT SPI FLASH IC

SMBUS ADDRESS : 0X49

FOXVILLE LAN CHIP

TIE TO GND DURING NORMAL OPERATION

GBE : I225 CHIP GBE PHY (FOXVILLE)

KEEP SHORT AND WIDE BETWEEN

CR-50 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE50

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 50 OF 80

INTEL CONFIDENTIAL
<>

2

1

C8C15

2

1

C8D2

2

1

C8C6

2

1

C8C4

2

1

C8D7

2

1

C8D3

2

1

R8E3

2

1

L8C1

2

1

R8E4

2

1

C8E2

8

7

6

5

4

3

2

1

U8E1

2

1

R8E6

2

1

R8E7

2

1

R8E1

2

1

R8E5

1

TP8C1

1

TP8D1

2

1

R2N18

2

1

C8C14

2

1

C8C8

2

1

C2N4

2

1

C8C7

2

1

C8C1

2

1

C8C12

2

1

C8C17

2

1

C8C5

2

1

C8D5

2

1

C8C9

2

1

C8C2

2

1

C8C10

2

1

C8D4

2

1

C8C3

EP

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32
31
30

29

28
27

26

25
24

23

22

21

20

19

18

17

16

15

14

13
12

11

10

9

8

7

6

5

4

3

2

1

U2N1

2

1

R2N15

2

1

R2P6

2

1

C2P1

2

1

R2N4

2

1

R8D2

2

1

R2N2

2

1

R2N3

2

1

R2N7

2

1

C2P2

2

1

C2P3

2

1

C2P4

2

1

R2P4

2

1

R2N1

2

1

R2N22

2

1

R2P9

2

1

R2P12

2

1

R2P10

2

1

R2P11

2

1

R8C3

2

1

R3N5

2

4

3

1

Y2M1

2

1

C3N1

2

1

C2N1

53C2

11C1

50A3

53C2

16C2

50A3

50A3

53C7

53C7

53C7

53C7

53C7

53C7

53C7

50A3

50C2

50C2

50C2

10A7

10C2

46A7

57A3

16C2

50C2

53C2

13C7

13C7

16A1

64B3

79B5

39B7

40C5

47A4

48A4

52A8

57A7

60A8

63A7

15C2

15C7

13C7

50C7

50C7

10A7

10D2

53C7

50C6

50C6

50A5

15C7

13C7

50A5

50A5

50A5

V3P3_A_LAN

V3P3_A_LAN

V3P3_A_LAN

V3P3_A_LAN

V3P3_A_LAN

V0P9_A_LAN1

V3P3_A_LAN

20PF

50V

0402LF C0G

5%

20PF

C0G

0402LF

50V

5%

D71700-057

XTAL
25MHZ
0.003%

5%

1M

1/16W

EMPTY
0402LF

10K 5%

CH

0402LF

5%

EMPTY

10K

0402LF

0402LF

0 5%

CH

0402LF
1/16W

RESN

1%

22K

0402LF EMPTY

0 5%

X5R

0.1UF

0402LF

10%

10%

X5R

0402LF

0.1UF

0.1UF

0402LF X5R

10%

0 5%

0402LF CH

1/16W

10K
5%

0402LF

CH

CH

10K
5%

1/16W

0402LF

1/16W

CH

1%

200

0402LF

0201LF

0 5%

EMPTY

0402LF X5R

10%

0.1UF

0201LF CH

0 5%

0

0

CH

0402LF

K63317-001

IC

X5R
0402LF
6.3V

22UF
20%

20%
X5R

22UF

6.3V

0402LF

X5R

22UF

6.3V

0402LF

20%

0201LF

X5R

10V

0.1UF
10%

20%

6.3V

X5R
0402LF

22UF

6.3V

20%
X5R

22UF

0402LF

10%

0.1UF

X5R
0201LF
10V

10%

0.1UF

X5R
0201LF
10V

10V

0201LF

X5R

10%

0.1UF

0201LF
10V

10%
X5R

0.1UF

10%

0.1UF

X5R

10V

0201LF

0.1UF
10%
X5R
0201LF
10V

10%
X5R
0201LF

0.1UF

10V

6.3V

22UF

X5R

20%

0402LF

5%
CH
0402LF

10K

1/16W

TP

TP

10K
1%

0402LF

CH

1/16W

5%
EMPTY

10K

1/16W

0402LF

CH
0402LF

10K

1/16W

1%

1%
CH
0402LF

10K

1/16W

IC

G69119-001

0402LF

X5R

10%

0.1UF

10V

10K

0402LF CH

1%

DFE201610E-1R0M

H90826-001

1.0UH

IND

10K
5%
CH

1/16W

0402LF

10V

10%
X5R
0201LF

0.1UF

0.1UF

0201LF

X5R

10%

10V

10V

10%
X5R

0.1UF

0201LF

X5R

10%

10V

0201LF

0.1UF

0201LF
10V

X5R

10%

0.1UF

10V

0.1UF
10%
X5R
0201LF

LAN1_LINK_1000

GPPC_E16_LAN_WAKE_N

GBE_XTAL_OUT

LAN1_LINK_2500

GPD_11_LANPHYPC

LAN_PWR_GOOD

GBE_JTAG_TDI

GBE_JTAG_TMS
GBE_JTAG_TDO

GBE_JTAG_CLK

GBE_JTAG_RSTN

GBE_XTAL_IN

LAN1_MDI0_DN

LAN1_MDI1_DN

LAN1_MDI1_DP

LAN1_MDI0_DP

LAN1_MDI3_DN

LAN1_MDI3_DP

LAN1_MDI2_DN

LAN_DEV_OFF_N

PCIE3_P7_RX_C_DN

PCIE3_P7_RX_C_DP

PCIE3_P7_TX_C_DN

PCIE3_P7_TX_C_DP

LAN_SPI_MISO

LAN_SPI_CS_N

LAN_SPI_CLK

LAN1_RESERVED

SML0_DATA

LAN1_0P9V_CTRL

GBE : I225 FOXVILLE

LAN_SPI_HOLD_N

GBE1_WAKE_N

PM_WAKE_N

LAN_SPI_MOSI

LAN_SPI_WP_N

LAN1_LINK_ACT

GBE_RBIAS

PCIE3_P7_TX_DP

PCIE3_P7_RX_DN

PM_PLTRST_N

CLK_P3_REQ_N

PCIE3_P3_CLK_DN

ULP_WAKE_N

PCIE3_P7_RX_DP

LAN_PWR_GOOD

LAN_DEV_OFF_N

SML0_CLK

LAN1_MDI2_DP

GBE_XTAL_OUT

GBE_XTAL_IN

LAN_SPI_MISO

PCIE3_P3_CLK_DP

PCIE3_P7_TX_DN

LAN_SPI_CS_N

LAN_SDP0

GBE_PHY_CAL

LAN_SPI_CLK

LAN_SPI_MOSI

CAD NOTE:

DESIGN NOTE:

DESIGN NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

T_POINT1

T_POINT1

OUT

SPI

POWER

I225

MDI

JTAG

LED

CRYSTAL

PCIE

SMBUSS

EP

+0.9V_A

+3.3V_A

MDI_C_P

XTAL_IN

PE_RX_N39

SMB_DATA

PHY_CAL

LED0

SMB_CLK

+3.3V_XO

+0.9V_CORE

XTAL_OUT

SPI_CS_N

PE_CLK_N

LAN_PWR_GOOD

PE_RX_P

MDI_B_P

MDI_A_P

MDI_A_N

MDI_B_N

+0.9V_A

MDI_C_N

+3.3V_A

MDI_D_P

MDI_D_N

+3.3V_PAD

LED2

LED1

ULP_WAKE_N

JTAG_TDO/MDI_LANE_SWAP

JTAG_TDI/SDP1

JTAG_CLK

RESERVED

+0.9V_A

+3.3V_CDB

+0.9V_CORE

+3.3V_DC

+0.9V_CTRL

+0.9V_CTRL

PE_CLKREQ_N

LAN_DISABLE_N

SPI_CLK

SPI_DOUT

SPI_DIN/AUX_PWR

SDP0

PE_RST_N

+3.3V_PAD

PE_WAKE_N

JTAG_TMS/SDP2

JTAG_RSTN

+3.3V_VPH

PE_TX_N

RBIAS

PE_CLK_P

PE_TX_P

+0.9V_VP

IN

IN
IN

IN

IN
IN

IN
IN

OUT

IN

OUT

OUT

BI

BI

IN
IN
IN

OUT

IN

OUT

IN
IN

OUT

OUT

IN

IN

IN

OUT

IN

OUT

W25Q16JVSNIQ

DI_IO0

CLK

HOLD_N

VCC

GND

WP_N

DO_IO1

CS_N

IN

OUT
OUT

OUT

OUT

IN

IN

IN

IN

tiger-html.html

PHYAD[2:4]:0X00

PHY ADDRESS

CONFIG_0

MAKE SURE 10 VALID CLOCK CYCLE

PRIOR TO DE-ASSERTING RESET PIN

CONFG_2

I2C MODE

CONFIG_1

NC

FIRMWARE LOAD MDIO

PHY : 88E2110

2MBIT SPI FLASH IC

0 : NORMAL MODE (DEFAULT)

FIRMWARE LOAD SPI

1 : FACTORY TEST

0 : PHYAD[0:1]->00

MDIO MODE (DEFAULT)

1 : PHYAD[0:1]->11

CLK OPTION
0 : 50MHZ XTAL1/2 (DEFAULT)
1 : 156.25MHZ CLKP/N

ISOLATE FROM AVSS

CR-51 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE51

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 51 OF 80

INTEL CONFIDENTIAL
<>

2

1

R2P13

2

1

R2P8

2

1

R2P14

2

1

R2N19

2

1

R2N16

2

1

R2N20

2

4

3

1

Y2N1

2

1

R2P2

2

1

R1P4

2

1

R1N6

2

1

R1N5

2

1

R1N4

2

1

R1P5

2

1

R1P2

2

1

R2R4

3

8

7

4

2

5

1

6

U2R1

1

TP9C2

1

TP9C1

1

TP2N2

1

TP2N1

2

1

R1P1

2

1

R1P3

2

1

R2P18

2

1

R2R3

2

1

R2R2

2

1

R2P16

2

1

R2P17

2

1

R1P7

2

1

R2N12

2

1

R2N9

2

1

R1N3

2

1

C2R1

2

1

R2P1

2

1

C1P1

2

1

C1P2

L8

L7

K8

K7

J8

J7

H8

G8

F8

F7

E8

E1

D8

D7

D2

D1

C8

C7

C6

C2
C1

B8
B7

B6

B2

B1

U1N1

2

1

R1P6

2

1

R2P5

2

1

R2P7

2

1

R2P15

2

1

C1P3

2

1

C1P4

N7
N6

N5

N4

N3

N2

M8

M5

M4

M1

L1

K2

K1

J2

J1

G7

G1

F1

E2

B5

B3

A7

A5

A3

U1N1

2

1

C2N3

2

1

C2N2

2

1

R2N6

2

1

R2N8

51B5

10C8

51D8

51C7

12B1

12B1
12C8

51B1

51C2

51B5

51A5

51A5

51B5

51B5

10C8

51B7

10C8

51D2

53B7
53B7

53B7
53B7

53B7

53C7

53B7

13C7

12B1

12B1

51C2

51B4

51C1
51B4

51B1

51C1

52A5

53B2

53C2

51B1
51B4

51B1
51B4

53B2

51A5

51A5

13C7

13C7

13C7

53B7

V3P3_A_LAN

V3P3_A_LAN

V3P3_A_LAN

VDDOM_LAN

VDDOM_LAN

VDDOM_LAN

AVSSC

AVSSC

AVSSC

V3P3_A_LAN

AVSSC

V3P3_A_LAN

V3P3_A_LAN

V3P3_A_LAN

0402LF

0

CH

0

1/20W

1%

4.99K

0402LF

EMPTY

1/16W

10PF

50V

0402LF

COG

5%

5%
COG

50V

10PF

0402LF

IC

88E2110

K20577-001

0.1UF

0402LF X5R

10%

0402LF

0.1UF 10%

X5R

1/16W

0402LF

1%

4.99K

CH

1/16W

CH
0402LF

1%

10K

1%

10K

1/16W

0402LF

CH

0402LF

EMPTY

5%

100

1/16W

88E2110

IC

K20577-001

0.1UF 10%

0402LF X5R

0402LF

0.1UF

X5R

10%

10K

CH

1%

0402LF
1/16W

X5R

10%

0.1UF

10V

0402LF

1/16W

1%

4.99K

CH
0402LF

100

CH

0402LF

1%

0402LF

100 1%

CH

5%

0402LF
1/16W

100

EMPTY

10K

0402LF
1/16W

1%
CH

1/16W

CH

1%

0402LF

10K

1%

10K

CH
0402LF
1/16W

0402LF

CH

4.99K
1%

1/16W

0402LF

CH

1%

4.99K

1/16W

EMPTY

1/16W

0402LF

49.9K
1%

1/16W

0402LF

1%
EMPTY

49.9K

TP

TP

TP

TP

D84927-001

W25X20CLSNIG

IC

1%

10K

0402LF CH

1%

0402LF

4.99K

CH

1/16W

1/16W

0402LF

CH

1%

4.99K

0 5%

CH

0402LF

0 5%

CH

0402LF

EMPTY

5%

0

0402LF

EMPTY

0

0402LF

5%

EMPTY

0402LF

5%

0

K22071-001

50MHZ

XTAL

1%
CH

1/16W

0402LF

10K

0

CH

5%

0402LF

0 5%

CH

0402LF

0

0402LF

CH

5%

5%
CH

10K

1/16W

0402LF

1%
EMPTY

1/16W

0402LF

10K

PHY : 88E2110

PHY_JTAG_TRST_N

PHY_JTAG_TMS
PHY_JTAG_TCK

PHY_SPI_WP_N

PHY_SPI_CS_N

PHY_TEST_POINT

PHY_TEST

PHY_REFCLK_DN

PHY_REFCLK_DP

GPPC_F18_SGMII_MDIO

PHY_CLKSEL_1

SGMII_INT_R

SGMII_INT

GPP_S1_SGMII_INT

CONFIG_1

88E2110_XTAL_1

88E2110_XTAL_2

PHY_JTAG_TDI

PHY_JTAG_TDO

PHY_SPI_CLK

PHY_IREF

PHY_SPI_MISO

PHY_SPI_CS_N

PHY_SPI_HOLD_N

PHY_SPI_MOSI

PHY_SPI_MISO

PHY_GPIO_1

PHY_REFCLK_R_DP
PHY_REFCLK_R_DN

PHY_SGMII_MDC
PHY_SGMII_MDIO

GPPC_F18_SGMII_MDIO

GPPC_F17_SGMII_MDC

PHY_CLKSEL_1

LAN2_MDI3_DP
LAN2_MDI3_DN

LAN2_MDI2_DP
LAN2_MDI2_DN

LAN2_MDI0_DN

LAN2_MDI0_DP

LAN2_MDI1_DP

SGMII_PPS_R

SGMII_AUXTS_R

SGMII_0B_RXP

SGMII_AUXTS

SGMII_PPS

CONFIG_1
CONFIG_2

CONFIG_2

PHY_GPIO_2

PHY_RST_N

PHY_RCLK

LAN2_LINK_ACT

LAN2_LINK_2500

CONFIG_2

CONFIG_1

LAN2_LINK_1000

PHY_SPI_CLK

PHY_SPI_MOSI

SGMII_0B_TXN

SGMII_0B_TXP

SGMII_0B_RXN

SGMII_0B_C_TXP
SGMII_0B_C_TXN

LAN2_MDI1_DN

SGMII_0B_C_RXN

SGMII_0B_C_RXP

DESIGN NOTE:

DESIGN NOTE:

DESIGN NOTE:

CAD NOTE:

DESIGN NOTE:

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT
OUT

BI
BI

BI
BI

BI

BI

BI
BI

IN

IN

OUT

OUT

2 OF 3

VDDCTRL

TEST

TSTPT

HSDACN

HSDACP

TRST_N

TCK

TMS

TDO

TDI

CONFIG2
CONFIG1
CONFIG0

MFIOS0

MFIOS1

MFIOS2

GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0

SPI_MISO

SPI_MOSI

SPI_SS_N

SPI_CLK

IN

IN

OUT

OUT

IN

CASE

IN

IN

OUT

OUT
OUT

OUT

IN

GND

VCC

CLK

HOLD_N

WP_N

CS_N

DI_IO0

DO_IO1

T_POINT1

1 OF 3

MDIO

CLK_SEL1
CLK_SEL0

INT_N

RESET_N

RCLK

XTAL2

XTAL1

CLKN

CLKP

IREF

SON

SOP

MDIN3

MDIP3

MDIN2

MDIP2

MDIN1

MDIP1

MDIN0

MDIP0

MDC

SIP
SIN

T_POINT1

T_POINT1

T_POINT1

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

tiger-html.html

PLACE CAP CLOSE

ISOLATE FROM AVSS

RD

NC

TO EACH PIN

0.88V : I-TEMP SKU(DEFAULT)

1A

PHY : 88E2110 PWR

0.8V : C-TEMP SKU

TRIPAD RA,RB AND RC,RD

RA

RB

PHY RESET

RC

CR-52 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE52

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 52 OF 80

INTEL CONFIDENTIAL
<>

2

1

R8D5

2

1

R8D7

2

1

R2N14

2

1

R2N11

2

1

R8C2

2

1

R8C5

2

1

FB8D1

2

1

R1P8

2

1

R2R1

2

1

C1R1

4

5

3

2

1

U1R1

1

TP9C3

2

1

C9D3

2

1

R1N1

2

1

C9C16

2

1

C8D6

2

1

C8D8

2

1

C9D8

2

1

C9C22

2

1

C9C23

2

1

C9D7

2

1

C9C10

2

1

R1N2

2

1

C8D17

7

6

5

4

3

2

1

EU8D1

2

1

R8E2

2

1

C8E1

2

1

FB8C1

2

1

FB9C1

2

1

C9C4

2

1

C9C1

2

1

C9C13

2

1

C9C9

2

1

C9C5

2

1

C9C8

2

1

C9C2

2

1

C9C3

2

1

C9C15

2

1

C9C11

2

1

C9C14

2

1

C9C12

2

1

C9C17

2

1

C9C7

2

1

C9C6

2

1

C9D2

2

1

C9D1

2

1

C9D4

2

1

C9D6

2

1

C9D5

2

1

C1N1

2

1

C8C11

2

1

C8C13

2

1

C8C16

2

1

C8D1

2

1

C9C19

2

1

C9C20

2

1

C8D9

2

1

C9D12

2

1

C9D11

2

1

C8D10

2

1

C9D10

2

1

C9C21

2

1

C9C18

2

1

C9D9

N8

N1

M7

M6

M3

M2

L6

L5

L4

L3

L2

K6

K5

K4

K3

J6

J5

J4

J3

H7

H6

H5

H4

H3

H2

H1

G6

G5

G4

G3

G2

F6

F5

F4

F3

F2

E7

E6

E5

E4

E3

D6

D5

D4

D3

C5

C4

C3

B4

A8

A6

A4

A2

A1

U1N1

16A1

64B3

79B5

39B7

40C5

47A4

48A4

50C7

57A7

60A8

63A7

12B1

51C7

V3P3_A_LAN

V3P3_A_LAN

V3P3_A_LAN

VDDOM_LAN

V1P8_A

V3P3_A_LAN

V1P8_A

V0P8_A_LAN2

V3P3_A_LAN

V3P3_A_LAN

AVSS

V1P8_A

V0P9_A_LAN2

AVSSC

V0P8_A_LAN2

K20577-001

88E2110

IC

0402LF
6.3V

0.22UF
20%
X5R

4V

0603LF

20%

47UF

X5R

0.22UF

0402LF

X5R

20%

6.3V

0402LF
6.3V

X5R

20%

0.22UF

20%
X5R

47UF

4V

0603LF

0603LF
4V

47UF

X5R

20%

4V

0603LF

X5R

47UF
20%

0402LF

20%

0.22UF

X5R

6.3V

6.3V

X5R

0.22UF
20%

0402LF

X5R

10%

0.1UF

10V

0402LF

10V

X5R

0.1UF
10%

0201LF

X5R
0201LF

10%

10V

0.1UF

10V

X5R

10%

0201LF

0.1UF

X5R

6.3V

20%

22UF

0402LF

6.3V

0402LF

20%

0.22UF

X5R

20%

4V

X5R

47UF

0603LF

10%

0.1UF

X5R

10V

0201LF

0402LF

20%

22UF

X5R

6.3V

0201LF

X5R

10%

10V

0.1UF

4V

X5R

47UF
20%

0603LF

20%

47UF

4V

0603LF

X5R

4V

0603LF

X5R

20%

47UF

0.1UF

10V

0201LF

X5R

10%

10V

X5R
0201LF

10%

0.1UF

22UF
20%
X5R
0402LF
6.3V

0402LF

22UF

6.3V

X5R

20%

0201LF

0.1UF
10%
X5R

10V

47UF

0603LF
4V

X5R

20%

0603LF

X5R

47UF

4V

20%

X5R

22UF
20%

0402LF
6.3V

10V

0201LF

10%

0.1UF

X5R

10%
X5R
0201LF
10V

0.1UF

20%

4V

47UF

X5R
0603LF

X5R

47UF
20%

0603LF
4V

X5R

22UF

6.3V

20%

0402LF

330

FB

1.5A

K81423-001

330

FB

1.5A

K81423-001

X5R

1UF
20%

0402LF
10V

0402LF CH

0

0

K63881-001

IC

10UF
20%

0402LF

X5R

10V

0

CH

0402LF

0

0402LF
6.3V

22UF
20%
X5R

10V

0201LF

X5R

0.1UF
10%

10V

0.1UF
10%

0201LF

X5R

0201LF

X5R

10%

0.1UF

10V

10V

0201LF

10%
X5R

0.1UF

0201LF
10V

X5R

10%

0.1UF

X5R

10%

0201LF
10V

0.1UF

10%
X5R

10V

0.1UF

0201LF

0

CH

0402LF

0

6.3V

0402LF

22UF
20%
X5R

TP

C78568-001

IC

0.1UF

10%
X5R

0402LF

10V

5%

10K

1/16W

0402LF

EMPTY

5%
CH
0402LF
1/16W

10K

1.5A
FB

330

K81423-001

0

0

50V

0603LF

CH

0603LF

0

50V

0
EMPTY

1/20W

0201LF

CH

0
1%

EMPTY
0201LF

0
1%

1/20W

0402LF
1/16W

1%

604

CH

5%

0402LF
1/16W

CH

1K

V0P8_A_LAN_FB

V0P8A_EN

SVID JUMPERS

V1P8_A_LAN_FB

V3P3_A_LAN_FB

PM_PLTRST_N

SGMII_RST_N

PHY : 88E2110 PWR

PHY_RST_N

LAN_VSEL_M

V0P8A_FB

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

CAD NOTE:

DESIGN NOTE:

CAD NOTE:

TLV75901PDRVT

THERMAL PAD

IN

DNC

EN

GND

FB

OUT

OUT

IN

IN

G

74AHC1G08

V

T_POINT1

3 OF 3

AVSSC

DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD

AVDDC

AVDDR

AVDDS

AVDDL

VSEL_M

VSEL_T

DNC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

VDDOT

VDDOM

VDDOL

VDDR09

AVDDT

AVDDT

AVDDH

AVDDH

AVDDL

tiger-html.html

PHY & GBE : RJ45 STACKED CONN

CR-53 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE53

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 53 OF 80

INTEL CONFIDENTIAL
<>

R10_B

R10_A

R9_B

R9_A

R8_B

R8_A

R7_B

R7_A

R6_B

R6_A

R5_B

R5_A

R4_B

R4_A

R3_B

R3_A

R2_B

R2_A

R1_B

R1_A

MT2

MT1

L4_B

L4_A

L3_B

L3_A

L2_B

L2_A

L1_B

L1_A

J2L1

2

1

C9B1

2

1

C7B1

2

1

R9A1

2

1

R9A2

2

1

R9A3

2

1

C7A1

2

1

C8A1

2

1

R8A1

2

1

R8A2

2

1

R8A3

51C4

51B2

51B2

50B3

50B3

50B3

50B3

50B3

50B3

51D4

51D4

51D4

51D4

51D4

51D4

51C4

50B3

50B3

50B6

50C6

50C6

51B2

V3P3_A_LAN

V3P3_A_LAN

249

0402LF CH

1%

1%

249

CH

0402LF

510

0402LF CH

5%

10%
X5R
0402LF

0.1UF

25V

X5R
0402LF
25V

0.1UF
10%

CH

5%

510

0402LF

1%

249

CH

0402LF

1%

0402LF

249

CH

10%

0402LF

0.1UF

EMPTY

X5R

10% 0.1UF

0402LF

K68691-001

CONN

LAN2_MDI0_DP

LAN2_VCC

LAN2_LINK_ACT

LAN2_LINK_2500

LAN1_MDI1_DN

LAN1_MDI2_DP

LAN1_MDI2_DN

LAN1_MDI3_DP

LAN1_MDI3_DN

LAN1_MDI1_DP

LAN2_MDI3_DN

LAN2_MDI3_DP

LAN2_MDI2_DN

LAN2_MDI2_DP

LAN2_MDI1_DN

LAN2_MDI1_DP

LAN2_MDI0_DN

LAN1_MDI0_DN

LAN1_MDI0_DP

LAN1_VCC

LAN2_LINK_ACT_R

LAN2_LINK_1000_R

LAN2_LINK_2500_R

LAN1_LINK_ACT_R

LAN1_LINK_1000_R

LAN1_LINK_2500_R

LAN1_LINK_ACT

LAN1_LINK_1000

LAN1_LINK_2500

LAN2_LINK_1000

RJ45 : RJ45 STACKED CONN

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

yellow

1000pF

2KV

0.1uF

0.1uF

0.1uF

0.1uF

75

75

75

J7

J8

SHIELD

J2

J5

J4

J6

J3

J1

75

YELLOW

GREEN

1000pF

2KV

0.1uF

0.1uF

0.1uF

0.1uF

75

75

75

J7

J8

SHIELD

J2

J5

J4

J6

J3

J1

75

GREEN

2TJRB2-AD-0001

GND

TD4-

TD4+

TD3-

TD3+

TD2-

TD2+

TD1-

TD1+

VCC

GND

TD4-

TD4+

TD3-

TD3+

TD2-

TD2+

TD1-

TD1+

VCC

+

-

-

+

+

-

+

-

MT2

MT1

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

OUT

OUT

OUT

IN

OUT

tiger-html.html

PLACE ESD CLOSE TO CONN

USB3 PORT 2

USB 3.1 : CMC & ESD 1

USB3 PORT 1

CR-54 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE54

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 54 OF 80

INTEL CONFIDENTIAL
<>

10

9

7

6

8

3

5

4

2

1

U3B1

10

9

7

6

8

3

5

4

2

1

U2B1

10

9

7

6

8

3

5

4

2

1

U8M1

2

1

R2B6

2

1

R2B5

2

1

R2B4

2

1

R2B3

2

1

C2C3

2

1

C2C4

4

3

2

1

L2B2

2

1

C2C1

2

1

C2C2

4

3

2

1

L2B1

2

1

R7M1

2

4

3

1

L7M1

2

1

R7M2

2

1

R3B6

2

1

R3B1

2

4

3

1

L3B1

56D4 54A8

56D4 54A8

54A6 56C4

56C4

13A7

56D4

13A7

54B5

56C4

56D1

13B7

56C1

13B7

54C1

56D1

54C1

56D1

54C5

56D4

54B1

56C1

54B1

56C1

54B5

56C4

54C5

56D4

54A6 56C4

56D1 54A8

13C2

13A7

13C2

54A6
56C1

13B7

13B7

13C2

54A6
56C1

13C2

56D1 54A8

13B7

90OHM

IND

752402-015

5%

0

0402LF EMPTY

5%

0

0402LF EMPTY

0

EMPTY

0402LF

5%

90OHM

IND

752402-015

5%

0

0402LF EMPTY

100MA NA

J16541-001

CHOKE

90OHM

X5R

10%

0402LF

0.22UF

0402LF

10%

X5R

0.22UF

90OHM

100MA NA

J16541-001

CHOKE

10%

0.22UF
0402LF X5R

X5R

0402LF

0.22UF 10%

5%

0

EMPTY

0201LF

5%

EMPTY

0201LF

0

EMPTY

5%

0

0201LF

0201LF

5%

0

EMPTY

H89865-001

IC

H89865-001

IC

H89865-001

IC

USB2_P1_C_DP

USB2_P1_C_DN

CONN_USB3_P1_TX_DP

USB3_P1_RX_DN

USB3_P1_RX_DP

CONN_USB3_P1_TX_DN

USB3_P2_RX_DP

USB3_P2_RX_DN

USB2_P2_C_DN

USB2_P2_C_DP

USB2_P1_C_DP

CONN_USB3_P2_TX_DP

CONN_USB3_P2_TX_DN

CONN_USB3_P1_TX_DP

USB2_P1_C_DN

USB3_P1_C_TX_DN

USB3_P2_C_TX_DN

USB3_P1_C_TX_DP

CONN_USB3_P1_TX_DN

USB2_P2_C_DP

USB2_P1_DP

USB3_P1_TX_DN

USB2_P2_DP

CONN_USB3_P2_TX_DN

USB3_P2_C_TX_DP

USB3_P2_TX_DP

USB3_P1_TX_DP

USB 3.1 : CMC & ESD 1

USB2_P1_DN

CONN_USB3_P2_TX_DP

USB2_P2_DN

USB2_P2_C_DN

USB3_P2_TX_DN

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

BI

BI

CHOKE_4P

BI

BI

BI

BI

BI

BI

CHOKE_4P

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

IN

IN

IN

IN

IN

IN

IN

tiger-html.html

USB 3.1 : CMC & ESD 2

USB3 PORT 4

USB3 PORT 3

PLACE ESD CLOSE TO CONN

CR-55 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE55

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 55 OF 80

INTEL CONFIDENTIAL
<>

10

9

7

6

8

3

5

4

2

1

U4B1

10

9

7

6

8

3

5

4

2

1

U3B2

10

9

7

6

8

3

5

4

2

1

U7M1

2

1

C3C3

2

1

C3C4

2

1

R3B5

4

3

2

1

L3C2

2

1

R3B4

2

1

R3B2

2

1

R3B3

4

3

2

1

L3C1

2

1

C3C1

2

1

C3C2

2

1

R4C1

2

4

3

1

L4C1

2

1

R4B1

2

1

R6M2

2

4

3

1

L6M1

2

1

R6M1

55B1

56A1

55C5

56A4

13C2

56A4 55A8

56A4 55A8

56A1 55A8

56A1 55A8

55A6 56A1

55A6 56A1

55A6 56A4

13C2

13B7

56A4

13B7

56A4

13B7

56A1

13B7

56A1

13B7

55C1

56A1

55C1

56A1

55B5

56A4

55B1

56A1

13B7

13B7

13B7

13C2

13C2

55B5

56A4

55C5

56A4

55A6 56A4

5%

0

0402LF EMPTY

752402-015

IND

90OHM

5%

0

0402LF EMPTY

5%

0

0402LF EMPTY

752402-015

90OHM

IND

5%

0

0402LF EMPTY

0.22UF
0402LF X5R

10%

0.22UF
0402LF X5R

10%

J16541-001

CHOKE

NA

100MA

90OHM

EMPTY

0201LF

5%

0

0201LF

0 5%

EMPTY

5%

0

0201LF EMPTY

CHOKE

J16541-001

NA

100MA

90OHM

0201LF EMPTY

5%

0

10%

0.22UF
0402LF X5R

10%

0.22UF
0402LF X5R

IC
H89865-001

IC
H89865-001

IC
H89865-001

CONN_USB3_P4_TX_DP

USB2_P3_C_DN

USB 3.1 : CMC & ESD 2

USB2_P3_DN

USB2_P3_C_DP

USB2_P3_C_DN

USB2_P4_C_DP

USB2_P4_C_DN

CONN_USB3_P4_TX_DN

CONN_USB3_P4_TX_DP

USB3_P3_C_TX_DN

CONN_USB3_P3_TX_DN

USB2_P3_DP

USB3_P3_TX_DN

USB3_P3_RX_DP

USB3_P3_RX_DN

USB3_P4_RX_DN

USB3_P4_RX_DP

USB2_P4_C_DN

USB2_P4_C_DP

CONN_USB3_P3_TX_DN

CONN_USB3_P4_TX_DN

USB3_P3_C_TX_DP

USB3_P3_TX_DP

USB3_P4_TX_DP

USB3_P4_TX_DN

USB3_P4_C_TX_DP

USB3_P4_C_TX_DN

USB2_P4_DN

USB2_P4_DP

CONN_USB3_P3_TX_DP

USB2_P3_C_DP

CONN_USB3_P3_TX_DP

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

4 Channel ESD

NC

GND

CH1
NC

GND

NC

CH4

CH3

NC

CH2

IN

BI

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

BI

BI

CHOKE_4P

BI

BI

BI

BI

CHOKE_4P

tiger-html.html

USB 3.1 : STACKED STD USB3.1 CONN X 2

STACKED STD USB3.1 CONN 1

STACKED STD USB3.1 CONN 2

CURRENT LIMIT = 2.0A

CURRENT LIMIT = 2.0A

CR-56 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE56

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 56 OF 80

INTEL CONFIDENTIAL
<>

2

1

R3A6

2

1

R3A4

2

1

R3A1

2

1

R4A4

2

1

R3A5

10

1

18

9

17

8

15

6

14

5

22

21

20

19

13

4

16

7

12

3

11

2

J7M1

10

1

18

9

17

8

15

6

14

5

22

21

20

19

13

4

16

7

12

3

11

2

J8M1

2

1

C3A4

2

1

C3A3

2

1

C3A1

2

1

R3A2

8

9

3

2

7

1

6

10

11

5

4

U3A1

2

1

R3A3

2

1

C3A2

2

1

C4A2

2

1

R4A1

2

1

R4A3

2

1

R4A2

2

1

C4A1

2

1

C4A3

2

1

C3A5

8

9

3

2

7

1

6

10

11

5

4

U4A1

55C5

55A8

55B5

55A6

13B7

55A4

13B2

29C8 13B2

13A7

54A4

54C1 54A8
54C1 54A8

13B7 54A4
13B7 54A4

54B1 54A6
54B1 54A6

54C5

54A8

54C5

54A8

13A7

54A4

54B5

54A6

54B5

54A6

55C1 55A8
55C1 55A8

13B7 55A4
13B7 55A4

55B1 55A6
55B1 55A6

55C5

55A8

13B7

55A4

55B5

55A6

V3P3_A

V3P3_A

V5_A

V5_A_USB1

V5_A_USB1

V5_A_USB2

V5_A_USB2

V5_A

IC

TPS2561

47UF
20%
X5R

10V

0805LF

47UF

X5R
0805LF
10V

20%

X5R
0402LF
25V

0.1UF
10%

CH
0402LF
1/16W

1%

28K

CH

5%

100K

0402LF

100K

5%
CH

0402LF

10%

0402LF

0.1UF

X5R

25V

0.1UF

X5R

25V

0402LF

10%

5%

0402LF

100K

CH

IC

TPS2561

G19827-001

1/16W

0402LF

CH

1%

28K

0402LF

10%

0.1UF

X5R

25V

10V

47UF
20%
X5R
0805LF

10V

47UF

0805LF

20%
X5R

USB3_SHLD_18P_4M

CONN

K64321-001

CONN

USB3_SHLD_18P_4M

K64321-001

5%

0402LF CH

0

5%

0

0402LF CH

5%
CH

100K

0402LF

CH

1/16W

0402LF

10K
1%

CH

1/16W

0402LF

10K
1%

USB2_P3_C_DP

CONN_USB3_P3_TX_DP

USB3_P3_RX_DN

GPPC_A16_USB2_OC3_N

USB2_OC1

USB2_1_EN2

USB2_1_EN1

USB2_1_ILIM

GPPC_E9_USB2_OC0_N

USB2_OC0

USB2_0_ILIM

USB2_0_EN2

USB2_0_EN1

USB3_P1_RX_DP

USB2_P2_C_DP
USB2_P2_C_DN

USB3_P2_RX_DP
USB3_P2_RX_DN

CONN_USB3_P2_TX_DP
CONN_USB3_P2_TX_DN

USB2_P1_C_DN

USB2_P1_C_DP

USB3_P1_RX_DN

CONN_USB3_P1_TX_DN

CONN_USB3_P1_TX_DP

USB 3.1 : STACKED STD CONN X2

USB2_P4_C_DP
USB2_P4_C_DN

USB3_P4_RX_DP
USB3_P4_RX_DN

CONN_USB3_P4_TX_DP
CONN_USB3_P4_TX_DN

USB2_P3_C_DN

USB3_P3_RX_DP

CONN_USB3_P3_TX_DN

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

BI

BI

FAULT2_N

FAULT1_N

OUT1

OUT2

EN2

ILIM

IN

EXPAD

GND

IN

EN1

IN

IN

OUT

OUT

IN

IN

OUT
OUT

OUT

OUT

UPPER

LOWER

SHLD

SHLD

GND_DRAIN

GND_POWER_RETURN

SSTX_M

SSTX_P

SSRX_M

SSRX_P

D_M

D_P

VBUS_POWER

SHLD

SHLD

GND_DRAIN

GND_POWER_RETURN

SSTX_M

SSTX_P

SSRX_M

SSRX_P

D_M

D_P

VBUS_POWER

UPPER

LOWER

SHLD

SHLD

GND_DRAIN

GND_POWER_RETURN

SSTX_M

SSTX_P

SSRX_M

SSRX_P

D_M

D_P

VBUS_POWER

SHLD

SHLD

GND_DRAIN

GND_POWER_RETURN

SSTX_M

SSTX_P

SSRX_M

SSRX_P

D_M

D_P

VBUS_POWER

BI
BI

OUT
OUT

IN
IN

BI
BI

OUT
OUT

IN
IN

BI
BI

FAULT2_N

FAULT1_N

OUT1

OUT2

EN2

ILIM

IN

EXPAD

GND

IN

EN1

tiger-html.html

ESATA PINOUT FOR TIGER ISLAND

SATA & ESATA : SATA PORT & PWR HEADER

NC

FOR SATA DOM

TRIPAD

SATA POWER_1

ONLY PCIE SIGNAL

SATA PORT_1

ESATA

CR-57 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE57

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 57 OF 80

INTEL CONFIDENTIAL
<>

2

1

R1J9

2

1

R1J8

2

1

C1H3

2

1

C1J1

2

1

C1J3

2

1

C1J2

2

1

R1J11

2

1

C1H2

P16

P15

P14

P13

P12

P11

P10

P9

P8

P7
P6

P5

P4

P3

P2

P1

MT6

MT5

MT4

MT3

MT2

MT1

J9W1

MH2

MH1

7

6
5

4

3

2

1

J9U1

2

1

C1G1

4

3

2

1

J1G1

2

1

C1G2

2

1

C9U1

2

1

C9U2

2

1

C9U4

2

1

C9U3

2

1

R1G5

2

1

R1G4

10A5

10D2

32A2

40C6

64B8

44A5

13A6

13A6

13A6
13A6

13D7

13D7
13D7

13D7

16A1

64B3

79B5

39B7

40C5

47A4

48A4

50C7

52A8

60A8

63A7

10A5

10D2

32A2

40C6

44A5

64B8

16C2

46A7 50C8 16C2

V5_S

V12_S

V5_S

V12_A

0

EMPTY

0

1/20W

0402LF

0
0
CH

1/20W

0402LF

0402LF X7R

10NF 10%

0402LF X7R

10NF 10%

0402LF

10NF

X7R

10%

X7R

10%

10NF

0402LF

0.1UF

0402LF
16V

X7R

10%

HDR

G84164-001

10%

0.1UF

X7R
0402LF
16V

CONN
H97660-001

K75383-001

CONN

10%

16V

X7R
0402LF

0.1UF

0 5%

CH

0402LF

0402LF

0.22UF 10%

X5R

10%

0.22UF
0402LF X5R

10%

0.22UF
0402LF X5R

10%

0.22UF
0402LF X5R

5%

0402LF

0

EMPTY

CH

5%

0

0402LF

ESATA_TX_C_DP

ESATA_RX_C_DN
ESATA_RX_C_DP

ESATA_PCIE_WAKE

SMB_SCL

ESATA_TX_DP

ESATA_TX_DN

ESATA_RX_DN
ESATA_RX_DP

SATA0_DOM

SATA0_TX_C_DP
SATA0_TX_C_DN

SATA0_RX_C_DP

SATA0_RX_DN

SATA0_TX_DP
SATA0_TX_DN

SATA0_RX_DP

SATA0_RX_C_DN

PM_PLTRST_N

ESATA_PLTRST_N

SMB_SDA

SATA & ESATA : SATA PORT/PWR HDR

GPD2_LAN_WAKE_N

PM_WAKE_N

ESATA_TX_C_DN

DESIGN NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

OUT

OUT

IN

OUT

IN

OUT

IN

BI

IN

ESATA

USB3.0

USB2.0

CONN_ESATA_RA

MT6

MT5

MT4

MT3

SSTX+

SSTX-

GND

SSRX+

SSRX-

GND

B+

B-

GND

A-

A+

GND

GND

D+

D-

VBUS

MT2

MT1

CONN_SATA_7P_SM_RA

MH2

MH1

GND

B+

B-

GND

A-

A+

GND

1X4HDR

OUT

OUT

IN

IN

tiger-html.html

PLACE CAPS NEAR PIN 25

PLACE CAPS NEAR PIN 38

HDA : AUDIO CODEC ALC 662 VD

TIED AT ONE POINT ONLY UNDER
THE CODEC OR NEAR THE CODEC

TRIPAD

5.1 CHANNEL HI-DEFINITION AUDIO CODEC

PLACE RES NEAR CODEC PIN

CR-58 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE58

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 58 OF 80

INTEL CONFIDENTIAL
<>

2

1

R1A7

2

1

R1B1

1

TP9N1

2

1

C1A3

2

1

C1C7

2

1

C9M3

2

1

C1C2

2

1

C1C3

2

1

C1C1

2

1

C9M4

2

1

C1C6

2

1

FB1C1

2

1

C1C4

2

1

R1B2

2

1

C1C5

2

1

C1B3

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20
19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

U1B1

2

1

C1B1

2

1

R9M2

2

1

R9M1

2

1

C1B2

2

1

R1B4

12D1

59A1

59C8

59B8

59A8

59C8
59C8

12D1

12D1

12D1

59C8

12D1

AGND_HDA

AGND_HDA

V5_A

V3P3_S

AGND_HDA

AGND_HDA

V5_HDA_LDO

AGND_HDA

V5_HDA_LDO

V3P3_S

V1P8_S

AGND_HDA

AGND_HDA

1%

CH

20K

0402LF

COG
0402LF

22PF
5%

0

0402LF CH

0

0402LF

0

CH

0

16V

0.1UF
10%
X7R
0402LF

G98139-100

IC

6.3V

10UF

0402LF X5R

20%

6.3V

X5R
0402LF

10UF
20%

CH

5%

33

0402LF

10%

0.1UF

X5R

10V

0402LF

600

0.5A
FB

16V

0.1UF

0402LF

X7R

10%

16V

10%
X7R
0402LF

0.1UF

X5R

0.1UF
10%

0402LF
10V

20%

10UF

X5R
0402LF
10V

0402LF

20%

10V

X5R

10UF

10V

X5R

10UF

0402LF

20%

10UF

10V

X5R
0402LF

20%

10UF
20%
X5R
0402LF

TP

1/20W

0
0

0402LF

CH

0

1/20W

0402LF

0

EMPTY

HDA_DVDDIO

HDA_V5A

GPP_R0_HDA_BCLK_R

SENSE_A
SENSE_B

HDA_JDREF

HDA_VREF

HDA_REG_REF

HDA_MIC1_VREFO_L

HDA_FRONT_R

HDA_FRONT_L

HDA_MIC1_L
HDA_MIC1_R

GPP_R4_HDA_RST_N_R

GPP_R1_HDA_SYNC_R

GPP_R2_HDA_SDO_R

HDA_MIC1_VREFO_R

GPP_R3_HDA_SDI

GPP_R3_HDA_SDI_R

HDA : ALC662_VD

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

IN
IN

T_POINT1

IN

OUT

IN

IN

IN

IN

IN

IN

alc662_vd

SPDIF-OUT

EAPD

DMIC-CLK

DMIC-DATA

LFE

CENTER

AVSS2

SURR-R

JDREF

SURR-L

LDO-OUT2

PIN37-VREFO

FRONT-R

FRONT-L

Sense B

LINE1-VREFO

MIC1-VREFO-R

LINE2-VREFO

MIC2-VREFO

LDO-IN

MIC1-VREFO-L

VREF

AVSS1

LDO-OUT1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

CD-R

CD-GND

CD-L

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

BEEP

RESET#

SYNC

DVDD-IO

SDATA-IN

DVSS

BITCLK

SDATA-OUT

GPIO1

REGREF

GPIO0

DVDD

IN

tiger-html.html

HDA : AUDIO JACK

CR-59 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE59

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 59 OF 80

INTEL CONFIDENTIAL
<>

2

1

R1A5

2

1

R1A6

MS

6

5

4

3

2

1

J9L1

C1A1

2

1

R1B3

2

1

C9M2

2

1

C9N1

2

1

R9M6

2

1

R9M4

2

1

FB9M2

2

1

C8N1

2

1

R9M5

2

1

FB9M1

2

1

R9M3

2

1

C9M1

2

1

C1A4

C1A5

2

C1A2

2

1

FB1A2

2

1

FB1A1

2

1

R1A3

2

1

R1A2

2

1

R1A4

2

1

R1A1

58A3

58B3

58A3

58A3

58B3

58A3

59A4

59C3

59B4

59C3

59B3

59B3

59A4

59B3

58B6

AGND_HDA

AGND_HDA

AGND_HDA

AGND_HDA

AGND_HDA

0402LF

2.2K

CH

5%

5%

2.2K

0402LF EMPTY

1%

75

0402LF CH

75 1%

CH

0402LF

2A

120

FB

2A

120

FB

50V

5%
COG

100PF

0402LF

X5R

4.7UF

0402LF

20%

X5R

20%

4.7UF

0402LF

50V

COG
0402LF

5%

100PF

1/16W

CH

5%

22K

0402LF

120

2A

FB

BLM18PG121SN1B

E49622-001

1%

75

CH

0402LF

X5R

20%

1206LF

100UF

120

FB

2A

22K

CH
0402LF
1/16W

5%

0402LF

75

CH

1%

X5R

20%

100UF

1206LF

0402LF

100PF

COG

5%

50V

0

0402LF

0

CH

50V

COG

5%

100PF

0402LF

CONN

H37313-001

1%

5.1K

0402LF RESN

1%

CH

20K

0402LF

HDA_FRONT_L

HDA_MIC1_VREFO_L

HDA_FRONT_R_C_R

HDA_FRONT_L_C_R

HDA_FRONT_L_C

HDA_FRONT_R_C

HDA_FRONT_R

HDA_MIC1_R_C_R

HDA_MIC1_L_C_R

HDA_MIC1_L_C

HDA_MIC1_R_C

HDA_MIC1_L

HDA_MIC1_VREFO_R

HDA_MIC1_R

CONN_FRONT_L

CONN_MIC_L

CONN_FRONT_R

CONN_FRONT_L

CONN_FRONT_R

CONN_MIC_L

JACK_DET

JACK_DET

SENSE_A

HDA : AUDIO JACK

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

IN

OUT

IN

OUT

AUDIOJACK_1PORT_7P

IN

OUT

IN

OUT

OUT

IN

IN

OUT

IN

IN

tiger-html.html

COM1_DTR_N--FAN_40_100

0: AT MODE

1: ATX MODE (DEFAULT;INT PU)

CONFIG STRAPS

1.8V : ESPI

ATX_AT_TRAP

0:ENABLE 80 PORT

1:FAN 40% PWM (DEFAULT;INT PU)

SUPER IO : F81804U

48MHZ

1:DISABLE 80 PORT (DEFAULT)

COM1_TX--80_TRAP#

0: REG 2E/2F (DEFAULT)

1: REG 4E/4F (INT PU)

COM1_RTS_N--CONFIG4E/2E

0:FAN 100% PWM

CR-60 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE60

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 60 OF 80

INTEL CONFIDENTIAL
<>

1

TP2J1

1

TP2H2

1

TP2H7

1

TP2H6

1

TP2H5

1

TP2H4

1

TP2H3

2

1

C2H2

4

3

1

2

Y2H1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

U2H1

2

1

R2H3

2

1

R1H3

2

1

R2H9

2

1

R2H4

1

TP9V1

1

TP9V2

2

1

R2H8

2

1

R2J14

2

1

R2J15

2

1

R8W3

2

1

R8V5

2

1

R1H2

2

1

R2J1

1

TP9W1

1

TP2H1

2

1

R2H2

2

1

R8V8

2

1

R8V7

2

1

C8W1

2

1

R8W1

2

1

R8W4

2

1

R2J9

2

1

C2H1

2

1

C1H1

2

1

R8V4

2

1

R2H5

2

1

R1H1

2

1

C8V4

2

1

R8W2

2

1

C8V5

2

1

C9W2

2

1

C9W1

2

1

C8W5

2

1

C8W3

2

1

C8W2

2

1

C8W4

2

1

R8V6

2

1

R2H7

2

1

R2H6

2

1

R8V9

V3P3_S

COM1_TX

5%

10K

1/16W

CH
0402LF

61B6

60C3

COM1_RX

COM1_TX

COM1_DSR_N

FANIN

SIO_ESPI_IO3

SIO_ESPI_IO0
SIO_ESPI_IO1
SIO_ESPI_IO2

SIO_ESPI_CLK

SIO_CLK_EN

PM_SLP_S4_N

ATX_AT_TRAP

COM1_RTS_N

COM2_DSR_N

COM2_RTS_N

SIO_KCLK

SIO_PSON_N

SIO_RSMRST_N

GPPC_E15_ESPI_ALERT

SIO_ESPI_CS_N

SIO_CLKIN

PM_SLP_SUS_N
WDT_RST_N

SIO_PWROK

SIO_DPWROK

PM_SLP_S3_N

SIO_CLK_PWR

SIO_CLKIN

SIO : F81804U

COM2_DTR_N

SIO_KDATA

COM1_DCD_N
COM1_RI_N

COM1_RTS_N

COM1_DTR_N

COM1_CTS_N

SIO_SUS_N

SLG_PWRBTN_SIO_IN

SIO_VREF

SIO_IFP

SIO_ESPI_RST_N

PM_PLTRST_N

COM2_RX

10%

0.01UF
0402LF X7R

48.000MHZ

OSC

K11200-001

IC

CH

0

CH

0

1/16W

0402LF

CH

5%

0

TP

TP

1K

0

CH

5%

0 5%

0402LF

EMPTY

TP

CH

0

0

0402LF

2M

0402LF
16V

0.1UF

X7R

10%

1/16W

0402LF

1K
1%
CH

X5R
0402LF
10V

0402LF
10V

10%
X5R

0.1UF

0402LF
10V

10%

0.1UF

X5R

10%

10V

X5R

0.1UF

0402LF

X5R

10V

10%

0402LF

0.1UF

X5R
0402LF

10%

10V

0.1UF

0402LF
10V

0.1UF

X5R

10%

10V

0402LF

0.1UF
10%
X5R

10V

0.1UF
10%

0402LF

X5R

0402LF

10%

0.1UF

X5R

10V

1/16W

5%
CH
0402LF

0

10K 5%

CH

5%

CH

10K

0402LF

0 0

CH

SIO_AGND

V3P3A_RTC

V3P3_A

V3P3_A

VDDQ_MEM

V5_A

V5_A

V3P3_A

SIO_AGND

V3P3_A

VSB3V

V3P3_S

V1P8_A

SIO_ESPI_RST_N

COM2_TX

1%

RESN

0402LF

V3P3A_RTC

0201LF

5%

K68695-001

SLG_PWRBTN_SIO_IN_R
SLG_PWRBTN_SIO_OUT

0402LF

1/16W

CH

4.7K

0402LF

CH

5%

1/16W

10K
1%
CH
0402LF

CH

5%

10K

0201LF
1/20W

1/16W

0402LF

4.7K
5%
CH

V3P3_A

CH

4.7K
5%

0402LF

V3P3_S

5%
CH

4.7K

1/20W

0201LF

WDT_RST_N
SIO_PWROK
SIO_BKLCTL
COM2_RTS_N

0402LF

5%

SIO_S3_N

V3P3_S

SLG_PWRBTN_SIO_OUT
SIO_RSMRST_N

0201LF

4.7K

5%

0402LF

1/16W

1/16W

SLG_PWRBTN_SIO_IN

1/16W

0402LF

CH

100K
5%

SIO_PECI

SIO_ESPI_IO3

SIO_ESPI_CLK

SIO_ESPI_RST_N

SIO_PECI

TP

SIO_ESPI_IO0

SIO_ESPI_IO1

SIO_ESPI_IO2

10%

0.1UF

61B3

61B6

60D3

61B4

63C8

63C8

60B2 10A1

60C2 10A1
60B2 10A1
60B2 10A1

60C2 10A1

77C6 69A7 68A8 65A1 79A7 64B3 16C7

60D3

60C3

62A3

62B3

62B4

79B4 60A3

11C1

60C2 10B1

60A8

79C8 67C8 66A8 79A5 16C7

65B8 60A3

78C8 78B8 60A3

78B2 77B8 75C8 75C3 75A8

75A3 71B1 71A7 69A7

79B7 64B3 16B6

60B7

61B6 60C3

62B3

62B4

62A3

61B4
61B4

61B6

60D3

61B6

60D3

61B4

78C1

60A3

60B7

61B6

60C7

60C2

10B1

63A7 57A7 52A8

50C7 48A4 47A4 40C5

39B7 79B5 64B3 16A1

62A3

60C2 60A6 10B1

62B7

45B8

60A3

16B5 60A3

65B8 60B7

78C8 78B8 60B7

45B8 60B3

62B7 62A3 60C3

16B5 60B7
79B4 60B7

60B8 78C1

60B3 22D6

60C7 10A1

60C7 10B1

60B7 10A1

60C7 60A6 10B1

60A4

22D6

60C7 10A1

60C7 10A1

60C7 10A1

62B3

62B4

5%

COM1_DTR_N

ATX_AT_TRAP

COM2_DCD_N

62B4

COM2_CTS_N

COM2_RI_N

SIO_COPEN_N

60A3

62B7

EMPTY
0402LF
1/16W

0402LF

65A4

SIO_BKLCTL

FAN_1_CTL

62A4

62A3

62B4

62A3 62B7

SIO_ESPI_CS_N

1%

560

0402LF
1/10W

RESN

1%

560

0402LF
1/10W

EMPTY

1%

560

0402LF
1/10W

EMPTY

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

DESIGN NOTE:

BI

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN
IN
IN

OUT
OUT

IN

BI

BI

BI

BI

IN

BI

IN

INH

OE/

TS/

OUT

V

GND

F81804U

ESPI_CS#/LFRAME#

GPIO51/SIN2/SEGE

GPIO50/RTS2#/SEGC

SIN1

SOUT1/80_TRAP#

DSR1#

RTS1#/CONFIG4E_2E

DTR1#/FAN_40_100

CTS1#

RI1#

DCD1#

3VCC

GPIO70/FANCTRL3/PWM_DAC3

FANIN3/GPIO97

FANCTL1/PWM_DAC1

FANIN1/GPIO95

3VSB

VIN1 (VCORE)

VIN2

VREF

D1+(CPU)

D2+

AGND

S5#/GPIO67

DPWROK/GPIO66

COPEN#

VBAT

RSMRST#/GPIO27

PWROK/GPIO26

PS_ON#/GPIO25

S3#/GPIO24

PWSOUT#/GPIO23

PWSIN#/GPIO22

5VSB (5VA)

PECI/GPIO17

BEEP/GPIO16/SDA

WDTRST#/GPIO15

GPIO14/ATX_AT_TRAP

GND

OVT#/GPIO12/SCL

KCLK

KDATA

GPIO94/MCLK/SDA

GPIO93/MDATA/SCL

I_VSB3V

SLP_SUS#/GPIO04

ERP_CTRL0#/GPIO00

GPIO92/GA20

GPIO91/KBRST#

CLKIN

ESPI_CLK/PCICLK

IFP

ESPI_IO3/LAD3

ESPI_IO2/LAD2

ESPI_IO1/LAD1

ESPI_IO0/LAD0

GPIO56/SPI_CLK/DTR2#/SEGD

ESPI_ALERT#/SERIRQ

GPIO53/DCD2#SEGG

ESPI_RESET#/LRESET# GPIO55/SPI_MOSI/CTS2#/SEGA

GPIO54/SPI_MISO/RI2#/SEGF

GPIO57/SPI_CS#/DSR2#/L#

GPIO52/SOUT2/SEGB

IN

IN

BI

T_POINT1

T_POINT1

OUT
OUT
OUT
OUT

IN

IN

IN

OUT

IN

BI

BI

BI

BI

IN

T_POINT1

T_POINT1

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

OUT

BI

OUT

IN

BI

BI

BI

BI

BI

BI

BI

tiger-html.html

1

0

1

1

SHUTDOWN

USE TRIPAD

1

1

RS422

1

MODE

RS485

RS485

0

0

0

0

0

0

0

1

1

0

CONFIG TABLE

1

1

M0

M1

M2

0

0

1

SIO : RS232 HEADER

RS232

M2M1M0: MODE 001 IS RS232

RS485

RS232

RS422

0

0

CR-61 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE61

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 61 OF 80

INTEL CONFIDENTIAL
<>

2

1

R9W1

10

9

8

7

6

5

4

3

2

1

J9Y1

2

1

R2J10

2

1

R1J7

2

1

R1K3

2

1

R1J10

2

1

C2K2

2

1

C2K9

EP

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12
11

10

9

8

7

6

5

4

3

2

1

EU2J2

2

1

C2J2

2

1

C2K6

2

1

C2K10

2

1

C2K5

2

1

R1K2

2

1

R1K1

2

1

R1K4

60C3

61B4

61B4

61B6

61B4

61B6

61B6

61B4

61B4

61D6

61A4

61A4

61D6
61D6
61D6

60C3

60D3

60C3

60D3

60C3

60D3

61A6

60C3

61A6

60C3

60C3
60C3

61A4

61A6

61B6

61B6

61B6

61B6

61A6

61A4

V5_S

V5_S

V5_S

0402LF
1/16W

EMPTY

1%

10K

0402LF

1%

10K

EMPTY

1/16W

1/16W

0402LF

10K

EMPTY

1%

10%
X5R
0402LF
25V

0.1UF

0.1UF

0402LF X5R

10%

16V

0402LF

X5R

10%

1UF

10%

0.1UF

0402LF X5R

K43785-001

IC

10%

X5R

0.1UF

0402LF

0402LF

0.1UF 10%

X5R

0402LF

CH

10K
1%

1/16W

0402LF
1/16W

CH

1%

10K

10K

1/16W

0402LF

EMPTY

1%

10K
1%

1/16W

0402LF

CH

H91845-001

HDR

CH

1/20W

0201LF

4.7K
5%

COM1_RX

HDR1_DCD_N

HDR1_RTS_N
HDR1_RI_N

HDR1_TX

HDR1_CTS_N

HDR1_DSR_N

HDR1_RX
HDR1_DTR_N

COM1_V_P
COM1_V_N

COM1_C1_N

COM1_C1_P

COM1_C2_N

COM1_C2_P

COM1_SLEW

HDR1_CTS_N

HDR1_DSR_N

COM1_MODE_0

COM1_MODE_1

COM1_MODE_2

COM1_RTS_N

COM1_TX

COM1_DTR_N

HDR1_RI_N

SIO : RS232 HEADER

COM1_DSR_N

HDR1_RTS_N

COM1_CTS_N

COM1_DCD_N
COM1_RI_N

HDR1_DTR_N
HDR1_DCD_N

COM1_SLEW

COM1_MODE_2

COM1_MODE_1

COM1_MODE_0

HDR1_TX

HDR1_RX

CAD NOTE:

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

2X5HDR

OUT

IN
IN

OUT

OUT

IN

IN
IN

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN

F81439A

EP

SINN

DCDN

NC

NC

MODE_1

NC

RTS#

SOUT

DTR#

RL#

SLEW

MODE_0

MODE_2

DCD#

SIN

CTS#

DSR#

NC

DTRN

SOUTN

CTSN

DSRN

NC

NC

NC

NC

V-

C2-

C1-

C2+

V+

C1+

NC

GND

VCC

RTSN

RIN

NC

VCC

NC

tiger-html.html

M2M1M0: MODE 011 IS RS485

USE TRIPAD

0

RS422

RS232

RS485

1

0

0

1

1

0

0

MODE

RS422

RS232

M2

CONFIG TABLE

0

1

0

1

RS485

0

0

0

0

1

0

1

M0

M1

1

1

1

RS485

0

1

SHUTDOWN

SIO : RS485/7 SEG HEADER

COMMON CATHODE

STUFF THE RES IF ENABLE 7 SEGMENT DISPLAY

7 SEGMENT DISPLAY DIRECT CONNECT TO HDR

CR-62 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE62

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 62 OF 80

INTEL CONFIDENTIAL
<>

2

1

R2J11

10

9

8

7

6

5

4

3

2

1

J8Y1

2

1

R2K2

2

1

R2J3

2

1

3

Q2J1

2

1

R8Y1

2

1

R2J8

2

1

R2J17

2

1

R2K4

2

1

R2J7

2

1

R8W5

2

1

R2K3

2

1

R8Y2

2

1

R2J5

2

1

R2J6

2

1

R2K1

2

1

R2J18

2

1

R2J13

2

1

C2K1

2

1

C2K7

EP

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12
11

10

9

8

7

6

5

4

3

2

1

EU2J1

2

1

C2K4

2

1

C2K3

2

1

C2J3

2

1

C2K8

2

1

R2J12

2

1

R2J16

60C3

62B4

62A3

60C3 62A4 62A3

60C3 62B3

62A1 62A7
62A1 62A4

62A1 62A4

62B1 62A7

62B7

62B7

62B7

62B7

60C3 62B3

60C3

62A3

60C3

62A3

62D6
62D6

62A4

62B1

62A7

62B1

60C3 62A3

62A1 62A7

62C1

62B1 62B7

62B1

62B7

62A1

62B4

62A1

62B4

62B1

62B4

62A1 62B4

62A1 62B4
62A1 62B3 62B7

60C3

62A4

62B4

60C3

62B7

60C3

62B4

60A3

60C3

62B7

60C3

62B7

60C3

62B4

60C3

62B4

60C3

62B4

62A4 62B4

62B4 62A7

62A4 62B3 62B7

62B4 62A7

62B4 62A4

62A4 62B7

62A7 62B7

62A7 62B4

62A1

62A4

62B7

62A4

60A3

60C3

62A3

62A1

62A4

62B3

62D6
62C6

60C3 62B3

V5_S

V5_S

V3P3_S

V5_S

1/16W

0402LF

EMPTY

10K
1%

10K

0402LF

1%

1/16W

EMPTY

0.1UF

0402LF X5R

10%

0402LF

10%

X5R

0.1UF

25V

0.1UF

0402LF

10%
X5R

0402LF
16V

1UF

X5R

10%

K43785-001

IC

0402LF

10%

0.1UF

X5R

X5R

0402LF

10%

0.1UF

CH

1/16W

0402LF

10K
1%

1%
EMPTY

10K

1/16W

0402LF

CH

1%

0402LF
1/16W

10K

CH

1%

0402LF
1/16W

10K

1/16W

10K
1%
EMPTY
0402LF

0

EMPTY

5%

0402LF

0

EMPTY

5%

0402LF

0

EMPTY

0402LF

5%

0

EMPTY

5%

0402LF

0 5%

EMPTY

0402LF

0

EMPTY

5%

0402LF

0

EMPTY

5%

0402LF

0 5%

EMPTY

0402LF

MOSFET

C81974-001

CH

5%

4.7K

0402LF
1/16W

0

0603LF CH

1A

H91845-001

HDR

5%

4.7K

0201LF
1/20W

CH

COM2_RX

COM2_RX

COM2_RI_N

HDR_7SEG_B_COM2_TX
HDR_7SEG_D_COM2_DTR_N

HDR_7SEG_E_COM2_RX_TXA

COM2_C2_P

HDR_7SEG_G_COM2_DCD_TXB_N

COM2_SLEW

COM2_MODE_2

COM2_MODE_1

COM2_MODE_0

COM2_DCD_N

COM2_DTR_N
COM2_TX

COM2_C2_N

COM2_MODE_0
COM2_MODE_1

HDR_7SEG_A_COM2_CTS_N

HDR_7SEG_F_COM2_RI_N

COM2_V_N

COM2_DSR_N

HDR_7SEG_C_COM2_RTS_N

HDR_7SEG_H_N

HDR_7SEG_A_COM2_CTS_N

HDR_7SEG_F_COM2_RI_N

HDR_7SEG_C_COM2_RTS_N

HDR_7SEG_B_COM2_TX

HDR_7SEG_G_COM2_DCD_TXB_N

HDR_7SEG_E_COM2_RX_TXA
HDR_7SEG_D_COM2_DTR_N
HDR_7SEG_L_N_COM2_DSR_N

V5S_COM2

COM2_V_P

COM2_C1_P
COM2_C1_N

SIO : RS485 HEADER

COM2_RX

COM2_TX

COM2_DSR_N

COM2_RTS_N

COM2_DTR_N

COM2_CTS_N

COM2_RI_N

COM2_DCD_N

HDR_7SEG_E_COM2_RX_TXA

HDR_7SEG_B_COM2_TX

HDR_7SEG_L_N_COM2_DSR_N

HDR_7SEG_C_COM2_RTS_N

HDR_7SEG_D_COM2_DTR_N

HDR_7SEG_A_COM2_CTS_N

HDR_7SEG_F_COM2_RI_N

HDR_7SEG_G_COM2_DCD_TXB_N

HDR_7SEG_L_N_COM2_DSR_N

HDR_7SEG_H_N

COM2_RTS_N

HDR_7SEG_L_N_COM2_DSR_N

COM2_MODE_2
COM2_SLEW

COM2_CTS_N

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

DESIGN NOTE:

OUT

2X5HDR

IN

OUT

IN

D

S

G

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN
IN

IN

OUT

IN

IN
IN

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT
OUT
OUT

OUT
OUT

IN

OUT

IN

IN

IN
IN

F81439A

EP

SINN

DCDN

NC

NC

MODE_1

NC

RTS#

SOUT

DTR#

RL#

SLEW

MODE_0

MODE_2

DCD#

SIN

CTS#

DSR#

NC

DTRN

SOUTN

CTSN

DSRN

NC

NC

NC

NC

V-

C2-

C1-

C2+

V+

C1+

NC

GND

VCC

RTSN

RIN

NC

VCC

NC

tiger-html.html

SMART FAN HEADER

MISC: UART HEADER/ LEDS INDICATOR/ SMART FAN

MTG HOLE

PLACE THESE RESISTORS CLOSE TO UART HDR

.

UART HEADER X 2

S5 RAIL LED STATUS

PLATFORM RESET LED STATUS

LED INDICATOR

CR-63 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE63

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 63 OF 80

INTEL CONFIDENTIAL
<>

2

1

DS9Y1

2

1

DS9Y2

10

9

8

7

6

5

4

3

2

1

J8U1

2

1

3

Q1K1

2

1

R8U6

2

1

R7U1

2

1

R8U5

2

1

R8U4

2

1

R3F10

2

1

R2F23

2

1

R2F24

2

1

R3F9

1

2

CR7W1

2

1

C7Y1

2

1

R7Y4

2

1

R7Y1

2

1

R7Y2

2

1

C7Y2

2

1

R7Y6

4

3

2

1

J7Y1

2

1

R7Y5

2

1

R7Y3

1

MH8J1

1

MH1A1

1

MH1K1

1

MH9D1

2

1

R9Y2

2

1

R9Y1

2

1

R9Y3

LED

0402LF

CH

V3P3A_LED

1/16W

40C5

V3P3A_LED_RST

V3P3A_LED_RST_R

GREEN
LED

GREEN

V3P3_A

52A8

48A4 47A4

V3P3_A

1/16W

C81974-001

MOSFET

5%

50C7

16A1

64B3

79B5

39B7

57A7

60A8

11C7 63A2

63A2 11C7

63A4 11C7

11C7 63A4

11C7 63A4

63A4 11C7

60B3

60B3

63A2 11C7

11C7

63A1

63A1

11C7

63B1

11C7

11C7

63B1

11C7 63A3

63A3 11C7

63B3 11C7

11C7 63B3

11C7 63A2

V3P3_S

V12_S

V5_S

V12_S

V3P3_A

V3P3_S

5%

0402LF
1/16W

1M

CH

CH

5%

3.3K

0402LF

3.3K

0402LF CH

0

0

1%

0402LF CH

100

HDR

A36295-009

1%

1/16W

10K

0402LF

CH

0603LF

10UF

20%
X5R

4.7K

CH

1%

0402LF
1/16W

RESN

0402LF

27K 1%

10K
1%
CH

1/16W

0402LF

16V

0402LF

X7R

10%

0.1UF

1N4148WS
SMLF

DIO

1%

49.9K

RESN
0201LF
1/20W

49.9K
1%
RESN

1/20W

0201LF

1/20W

49.9K
1%
RESN
0201LF

RESN

1%

1/20W

0201LF

49.9K

49.9K

1/20W

0201LF

1%
RESN

RESN
0201LF

1%

49.9K

1/20W

1%

49.9K

RESN

1/20W

0201LF

1%
RESN
0201LF

49.9K

1/20W

HDR

H91845-001

PM_PLTRST_N

UART2_TXD

UART2_RXD

UART1_CTS

UART1_RTS

UART1_TXD

UART1_RXD

FANIN

FANIN_R

HDR_FANIN_R
HDR_FAN_1_CTL

FAN_1_CTL

UART2_CTS

UART1_RTS

UART1_CTS

UART1_RXD

UART1_TXD

MISC : HDR/LEDS/FAN

UART2_RTS

UART2_CTS

UART2_RXD

UART2_TXD

UART2_RTS

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

IN

OUT

OUT

IN

IN

OUT

OUT

IN

MTG_HOLE_1P

MTG_HOLE_1P

MTG_HOLE_1P

MTG_HOLE_1P

IN

2X5HDR

D

S

G

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

1X4HDR

tiger-html.html

B2B CONN : 80 PIN I/O

FOR DEBUG PURPOSES

CLOSE TO EDGE OF BAORD

PULL UP SDA/SCL AT IO BOARD

TRIPAD, PLACE NEAR TO B2B CONN

MPN : ERF5-040-07.0-L-DV-TR

CR-64 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE64

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 64 OF 80

INTEL CONFIDENTIAL
<>

2

1

R9P13

2

1

R9P11

2

1

R9P12

2

1

R9P14

2

1

C1D9

2

1

C1D10

1

TP7U1

1

TP8U1

1

TP8U2

2

1

C1E4

2

1

C1E3

2

1

C9R6

2

1

C9R4

2

1 R9P2

2

1 R9P4

2

1

R9P5

2

1

R9P8

2

1

C9R2

2

1

C9R3

2

1

C1E5

2

1

C1E6

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

J9P1

11C8

11C8

11C8

11C8

7B8

10D2

28A8

16B6 79B7 60B7 65A4 69A7 71A7 71B1 75A3 75A8 75C3
75C8 77B8 78B2

10A5

10D2

32A2

40C6

44A5

57A7

16C7 79A7 60B7 65A1 68A8 69A7 77C6

10A5

10D2

32A2

40C6

44A5

57A7

16A1 79B5 39B7 40C5 47A4 48A4 50C7 52A8 57A7 60A8
63A7

65A1 65A6

65A4 65B5

11B7 64A4

11B7 64A4

15C7

11B7 64A2

15C7

11B7 64A2

12A3

13D2

12A3

13D2

13C2

13C2

15C7

64A5

15C7

64A5

13C7

7C2

13C7

7C2

7C2

7C2

15C7

7C2

15C7

7C2

13A6

7C2

13A6

7C2

11C7

11C7

11C7

15C2

11C7

15C2

13A6

13A6

13C7

12A3

64B3

7C2

7B8

29B5

64B3

7B8

7C2

11B7

64B3

11B7

64B3

11B7

64B3

12A3

11B7

64B3

13C7

V1P8_A

V12_A

V12_A

V3P3_S

V3P3_S

V3P3_A

CONN

K72511-001

0402LF

10%
X7R

16V

0.1UF

0402LF
16V

0.1UF
10%
X7R

16V

0402LF

0.1UF

X7R

10%

16V

0.1UF

0402LF

10%
X7R

1/16W

1K

CH
0402LF

1%

1%
CH

1K

0402LF
1/16W

1/16W

1%

1K

CH
0402LF

1/16W

1K

0402LF

CH

1%

0402LF

0.22UF 10%

X5R

0402LF X5R

0.22UF 10%

10%

0.22UF
0402LF X5R

0.22UF
0402LF

10%

X5R

10%

X5R

0402LF

0.22UF

0.22UF
0402LF X5R

10%

EMPTY

0 5%

0402LF

5%

EMPTY

0402LF

0

CH

0402LF

5%

0

0402LF CH

0 5%

PCIE3_P10_TX_C_DP

GPPC_B19_SPI1_CS0

GPPC_B21_SPI1_MISO

GPPC_B22_SPI1_MOSI_R

GPPC_B20_SPI1_CLK_R

DDSP_HPD3

GPPC_C2_SMBALERT_N

PM_SLP_S3_N

SMB_SDA

PM_SLP_S4_N

SMB_SCL

PM_PLTRST_N

FP_SYSRST_N

FP_PWRBTN_N_R

I2C3_SCL

I2C3_SDA

PCIE4_CLK_DP

I2C2_SCL

PCIE4_CLK_DN

I2C2_SDA

PCIE4_0_RX_DP

USB2_P8_DN

PCIE4_0_RX_DN

USB2_P8_DP

USB2_P7_DN

USB2_P7_DP

PCIE3_P5_CLK_DN

DDP3_SDA_TCP2_AUX_DN

PCIE3_P5_CLK_DP

DDP3_SCL_TCP2_AUX_DP

PCIE3_P10_RX_DN

TCP2_TX1_DN

PCIE3_P10_RX_DP

TCP2_TX1_DP

PCIE3_P10_TX_C_DN

TCP2_TX0_DN

TCP2_TX0_DP

PCIE3_P4_CLK_DN

TCP2_TXRX1_DN

PCIE3_P4_CLK_DP

TCP2_TXRX1_DP

PCIE3_P9_RX_DN

TCP2_TXRX0_DN

PCIE3_P9_RX_DP

TCP2_TXRX0_DP

PCIE3_P9_TX_C_DN

UART0_RTS

PCIE3_P9_TX_C_DP

UART0_CTS

UART0_RXD

CLK_P5_REQ_N

UART0_TXD

CLK_P4_REQ_N

PCIE3_P9_TX_DN

PCIE3_P9_TX_DP

PCIE3_P10_TX_DP

PCIE4_0_TX_DN

DDP3_SCL_TCP2_AUX_DP

TCP2_AUX_DP

GPPC_D10_DDP3_SDA

DDP3_SDA_TCP2_AUX_DN

GPPC_D9_DPP3_SCL

TCP2_AUX_DN

I2C2_SCL

I2C2_SDA

I2C3_SDA

PCIE4_0_TX_DP

UART2_RXD

UART2_TXD

I2C3_SCL

PCIE3_P10_TX_DN

B2B CONN : 80 PIN IO B2B

CAD NOTE:

DESIGN NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

BI

BI

BI

BI

BI

BI

OUT

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN

OUT
OUT

IN

IN

IN

BI
BI
BI

BI

BI

BI

BI

BI

BI

OUT

BI

BI

BI

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

OUT
OUT

OUT

ERF5-040-xx-L-DV-TR

tiger-html.html

RESET BTN

FRONT PANAL HDR

RTC BATT IPN:D81197-001

POWER BTN

POWER JACK

PWR : V12_IN/RTC/BTN

RTC GENERATION

POWER & RESET FRONT PANEL

CR-65 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE65

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 65 OF 80

INTEL CONFIDENTIAL
<>

2

1

R2B2

2

1

C8M1

2

1

C8M2

2

1

R2B1

S2

S1

3

2

1

JP2A1

S2

S1

3

2

1

JP2A2

10

9

8

7

6

5

4

3

2

1

J8M2

2

1

R8M1

2

1

3

CR2B1

MT4

MT3

MT2

MT1

2

1

J1R1

2

1

C8F3

2

1

CR2A1

2

1

R2A3

2

1

R8L1

2

1

C8L1

2

1

CR2A2

4

3

2

1

U2A1

3

1

2

CR2C1

2

1

J8N1

2

1

C1T2

2

1

F1T1

2

1

C8F4

2

1

C2C5

R2C3

2

1

R2A2

2

1

R2A1

2

1

C2A1

3
2

1

J1R2

2

1

C1T1

10C8

64B3

65B5

16B6

64B3

79B7

60B7

69A7

71A7

71B1

75A3

75A8

75C3

75C8

77B8

78B2

64B3

65A4

65A8

78C8

64B3 65A6

16C7 64B3 79A7 60B7 68A8

69A7 77C6

65B8

16C7 79A4

16C7

64B3 65A1

60A3

60B7

V12_A

V12_ADP

V3P3_A

V3P3A_RTC

V3P3_A

V12_ADP

V3P3_S

V3P3_A

V3P3_S

VRTC_BATT

V5_S

V3P3_S

0.1UF

X7R
0603LF
25V

10%

H17606-001

CONN

0.1UF
10%

10V

0402LF

X5R

CH

0

0402LF

0

CH

1%

10K

1/16W

0402LF

1K

CH

5%

0402LF

0402LF
6.3V

20%
X5R

1UF

X5R

10%

25V

0603LF

1UF

FUSE

6.3A

X5R

10%

10UF

0805LF
25V

G93901-001

HDR

BAT54C

DIO

C52251-001

C76261-001

IC

4A

SM

4A

DIODE

H97212-001

50V

0.01UF
10%
X7R
0402LF

0402LF

1%

100K

CH

1/16W

1/16W

10K
1%
CH
0402LF

DIODE

SM

4A

4A

H97212-001

100UF

20%

25V

TANT

7343LF

K67505-001

CONN

D77096-001

MMBD717LT1
DIO

1/16W

10K

CH
0402LF

5%

H91845-001

HDR

HDR

K31949-001

HDR

K31949-001

0

EMPTY

0201LF

1%

X5R

0.1UF

0201LF

10%

10V

0201LF

0.1UF
10%
X5R

10V

10K

0402LF
1/16W

CH

1%

GPPC_E8_SATA_LED_N

FP_PWRBTN_N_R

PM_SLP_S3_N

FP_PWRBTN_N_R

MASTER_RST_N

HDR_RTC_BATT

FP_PWRBTN_N

FP_SYSRST_N

PM_SLP_S4_N

PWR : V12_IN/RTC/BTN

MASTER_RST_N

PM_SLP_S5_N

SYS_RST_N

FP_SYSRST_N

WDT_RST_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

tact_switch_5p-O

IN

IN

tact_switch_5p-O

IN

IN

IN

IN

IN

2X5HDR

IN

IN

IN

OUT

2x1HDR_UMPS

MT4

MT3

MT2

MT1

2

1

MAX6816

GND

OUT

IN

VCC

SOT23C

1X2HDR

OUT

PWR_JACK

1

2

3

OUT

tiger-html.html

OUTPUT VOLTAGE: 5.0V

MAX LOAD CURRENT: 6A

SOFT START: 0.91MS

SW FREQ: 355KHZ

SOFT START: 0.91MS

SW FREQ: 300KHZ

7A

ISAT:12.2A

6A

PWR : V5_A/V3P3_A

ISAT:15.9A

MAX LOAD CURRENT: 7A

OUTPUT VOLTAGE: 3.3V

Not supply the system

V3P3_REG Enable TPS51225C

V3P3_REG and V5_REG are always-on regulators

CR-66 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE66

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 66 OF 80

INTEL CONFIDENTIAL
<>

2

1

R1E3

2

1

R2E1

2

1

R9P6

2

1

C9R5

13

3

14

12

4

2

19

9

17

21

8

18

7

6

20

11

15

10

16

5

1

U9N1

8

7

6

1

4

3

9

5

U1D1

R1D1

2

1

L1C3

2

1

C8T1

2

1

C8P5

2

1

C8R1

2

1

C9R1

2

1

L8R1

2

1 R9P15

2

1 R9P10

R8R2

C8R3

2

1

R9P9

2

1 R9P3

8

7

6

1

4

3

9

5

U8R1

2

1

R9P7

2

1

C9P1

2

1

C1C9

2

1

C9N3

2

1

C9N4

2

1

C1C8

2

1

C9N2

2

1

R9N1

2

1 R9N2

2

1

C1E2

2

1

C1E1

C1D11

2

1

R8N1

2

1

R8N2

2

1

L2E1

2

1

C1D8

2

1

C8P1

2

1

C2D9

1

TP9N2

2

1

R9P1

2

1

R8P1

67B8 78D8 79D8

16C7

79A5

60B7

67C8

79C8

VCC12_A

V3P3_REG

V3P3_REG

V12_A

V3P3_A

V3P3_A

V5_A

V3P3_REG

VCC12_A

V12_A

V5_REG

EMPTY

0

0

0402LF

1/16W

0402LF

10K

CH

5%

X5R

10%

0402LF
25V

0.1UF

10V

TANT

20%

7260LF

330UF

IHLP2020BZERR22M01

0.22UH

IND

1%

10K

CH

1/16W

0402LF

0402LF

1/10W

CH

15K

1%

X7R
0402LF

820PF

50V

10%

X5R

25V

10%

0805LF

10UF

22UF
20%
X5R

25V

0805LF

0603LF

1%

29.4K

CH

1/10W

CH

0402LF

2.2 1%

10%

X5R

0402LF

0.1UF

10%

X5R

25V

0.1UF

0402LF

1UF

X5R

10V

10%

0402LF

0402LF

X5R

10V

10%

1UF

25V

10%

X5R

0402LF

0.1UF

X5R

10%

0402LF

25V

0.1UF

0402LF

5%

4.7K

EMPTY

1/16W

IC
G20630-001

CH
0603LF

29.4K
1%

1/10W

2.2 1%

CH

0402LF

820PF

0402LF
50V

10%
X7R

CH

1%

2.2

0402LF
1/16W

10K

CH

1%

0402LF
1/16W

1/10W

0603LF

CH

1%

6.49K

IND

2.2UH

G95253-001

22UF
20%
X5R
0805LF
25V

0805LF

10UF

X5R

25V

10%

0.1UF

25V

X5R

10%

0402LF

7343LF

10%

220UF

TANT

10V

1/16W

CH

2.2

1%

0402LF

IC

G20630-001

IC
G60788-001

0402LF

X5R

0.1UF

25V

10%

10K

5%
CH

0402LF

1/16W

2512LF

0.001

CH

1W

1%

2512LF

0.001
1%

1W

CH

V5A_V3P3A_VR_PWRGD

V3P3A_DRVH2

V3P3A_L_R

V3P3A_VFB2

3.3UH

V5A_L

G74689-001

IND

V5A_VBST1_C

V3P3A_SW2

V3P3A_VBST2_C

V5A_DRVH1

V5A_VFB1

V5A_VO1

V5A_DRVL1

V5A_L_R

PM_SLP_SUS_N

25V

0.1UF

PWR : V5_A/V3P3_A

10%
X5R
0402LF

EN_V3P3_A

V5A_VBST1

V5A_SW1

V5A_CS2

V3P3A_L

V3P3A_VBST2

EN_V5_A

V5A_CS1

V3P3A_DRVL2

TP_V5A_VCLK

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

DESIGN NOTE:

OUT

TPS51225C

DRVL1

SW1

VBST1

DRVH1

VIN

VO1

VCLK

VREG5

EN1

CS1

VFB1

VREG3

EN2

THERMAL_PAD

CS2

VFB2

DRVL2

SW2

VBST2

DRVH2

PGOOD

CSD87331Q3D

VIN1_VIN2

PGND

TGR

BG

TG

VSW

VSW

VSW

T_POINT1

CSD87331Q3D

VIN1_VIN2

PGND

TGR

BG

TG

VSW

VSW

VSW

IN

tiger-html.html

PLACE 0.1UF CAP NEAR TO THE IC

SW FREQ: 700KHZ

PWR : V1P8_A

OUTPUT VOLTAGE: 1.8V

ISAT:7.1A

MAX LOAD CURRENT: 4.5A

SOFT START: 0.4MS

4.5A

CR-67 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE67

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 67 OF 80

INTEL CONFIDENTIAL
<>

2

16

15

14

13

1

12

11

10

9

3

17

8

7

5

4

6

EU8P1

2

1

C8P2

2

1

R8P2

2

1

R8P4

2

1

L3D1

2

1

C8R2

2

1

R8P6

2

1

R8R1

2

1

C3D5

2

1

C3E2

2

1

C3E1

2

1

C8R5

2

1

R3D10

2

1

R8P3

2

1

C7R1

2

1

R7P11

2

1

C8P4

2

1

C8P3

2

1

R8P5

2

1

C8R6

2

1

C8R4

2

1

C7R2

2

1

R8R3

66C3

78D8

79D8

70B3 79C8

16C7

79A5

60B7

66A8

79C8

V12_A

V1P8_VR_OUT

V3P3_A

V1P8_A

V3P3_A

1A

CH

0

0805LF

0.1UF

X5R

10%

25V

0402LF

0805LF

20%

25V

X5R

22UF

20%

10UF

25V

X5R
0603LF

0

0

CH

0402LF

50V

0402LF

X7R

10%

1000PF

1UF

X5R

10%

16V

0402LF

0 0

CH

0402LF

10%

X5R

10V

0402LF

0.22UF

5%
CH

100K

1/16W

0402LF

CH

0805LF

1%

0.01

20%
X5R
0603LF

47UF

6.3V

X5R
0603LF

20%

47UF

6.3V

6.3V

20%

47UF

X5R
0603LF

25V

0.1UF
10%

0402LF

X5R

27K

RESN
0402LF

1%

1/16W

1%

0402LF

CH

20K

1/16W

50V

22PF

0402LF

COG

5%

20%

1.5UH

IND

E76684-006

5.2A

0

EMPTY

5%

0402LF

1%

0402LF
1/16W

EMPTY

100K

10%

0402LF
25V

EMPTY

0.1UF

TPS54426

IC

G58514-001

V1P8A_VIN

V1P8A_VR_EN

V1P8A_PHASE

V1P8A_VR_FB

V5A_V3P3A_VR_PWRGD

V1P8A_VBST

V1P8A_PWRGD

V1P8A_VREG5

V1P8A_SS

V1P8A_VBST_R

PM_SLP_SUS_N

PWR : V1P8_A

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

POWERPAD

VO

VIN3

VIN2

VIN1

VBST

SW3

SW2

SW1

PGND2

PGND1

EN

PG

GND

SS
VREG5

VFB

IN

OUT

IN

tiger-html.html

15A

VDD2 ENABLE SIGNAL GENERATION

FEEDBACK COMPENSATION CIRCUIT

MAKE PIN 3 & 5 40 MIL TRACE

SW FREQ: 635KHZ

ISAT:41A

PWR : VDDQ_MEM/VDDQ_VTT

OUTPUT VOLTAGE: 1.2V

MAX LOAD CURRENT: 15A

SOFT START: 550US

CR-68 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE68

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 68 OF 80

INTEL CONFIDENTIAL
<>

2

1

L7U1

2

1

R7V3

2

1

C7V7

2

1

C3G1

2

1

R3G1

2

1

C7V2

2

1

C7V1

2

1

R3H7

2

1

R7V5

2

1

R7V2

2

1

R7W1

2

1

C7V9

4

5

1

3

2

U7V1

2

1

R3G3

1

2

CR3G1

2

1

R3G6

2

1

R3G4

2

1

R3G5

2

1

R3H4

2

1

R3H5

2

1

R3H1

2

1

R3G2

2

1

C6U1

2

1

C6V2

2

1

C6U3

2

1

R3G7

2

1

R7U3

2

1

C7V3

8

7

6

1

4

3

9

5

U3G1

2

1

C3G4

2

1

C3G6

2

1

C3G3

2

1

C3G5

2

1

R3H6

2

1

C7V6

2

1

C7V8

2

1

R7V1

2

1

C7V5

2

1

C7V4

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

EU7V1

2

1

R3H2

2

1

C3G2

2

1

C3G7

2

1

C3H2

2

1

C3H1

2

1

C6U2

2

1

C7U1

VDDQ_MEM_OUT

CH

1206LF

0 1A

INDUCTOR

0402LF

X5R

10%

1UF

68A1

68B4

68A5

68B6

72A4

79D4

69B8

69C5

79D4

68D8 72A4 79D4

8A3

68C6

68B8

68B8

16C7

64B3

79A7

60B7

65A1

69A7

77C6

V12_A

VDDQ_MEM

V3P3_A

VDDQ_VTT_OUT

VDDQ_VTT

V5_A

V3P3_S

VDDQ_MEM

VDDQ_MEM

VDDQ_MEM

VDDQ_MEM

25V

X5R

20%

4V

1206LF

220UF

0.01UF
10%
X7R

50V

0402LF

10%
EMPTY

50V

2200PF

0402LF

50V

X7R

10%

4700PF

0402LF

X5R

0.1UF
10%

0402LF
25V

0

CH

0402LF

5%

IC

H41785-001

6.3V

X5R

10UF

0402LF

20%

20%

10UF

6.3V

0402LF

X5R

143K 1%

RESN

0402LF

0402LF

0.1UF
10%
EMPTY

25V

X7R

0.033UF
10%

0402LF
16V

RESN
0402LF
1/16W

562K
1%

20%

25V

22UF

0805LF

X5R

20%

22UF

0805LF
25V

X5R

X5R

25V

22UF
20%

0805LF

22UF
20%
X5R

25V

0805LF

G53132-001

IC

0.1UF 10%

X5R

0402LF

0
5%
EMPTY
0402LF
1/16W

20%

1206LF
4V

X5R

220UF

X5R
1206LF
4V

220UF
20%

X5R

4V

1206LF

20%

220UF

5%

0

0402LF CH

1/10W

0603LF

CH

1%

12K

0

CH

5%

0402LF

CH

1%

20K

0402LF
1/16W

0 5%

0402LF EMPTY

0

CH

0402LF

5%

CH

0402LF

5%

100

1N5819HW

D55839-001

DIO

SMLF

CH

0402LF

5%

10K

IC
G58837-001

X5R

25V

10%

0.1UF

0402LF

0

CH

5%

0402LF

CH

100K

0402LF

1%

1/16W

0

CH

0402LF

5%

0 1A

CH

0603LF

20%

0402LF

10UF

X5R

6.3V

20%

0402LF
6.3V

10UF

X5R

0402LF
1/16W

1K
1%
EMPTY

2200PF

EMPTY

50V

10%

0402LF

X5R

20%

2.2UF

10V

0402LF

CH

100K

1/16W

1%

0402LF

21A

20%

H38521-001

0.3UH

DDR_VTT_PG_CTRL

VDD2_LGATE

VDD2_VR_VTTREF

VDD2_VR_FB

VDD2_VR_CS

VDD2_VR_EN

VDD2_UGATE

VDD2_VR_PWRGD

VDD2_VR_BST

VDD2_VR_VIN_R

VDD2_VR_PHASE

VPP_VR_PWRGD

VDD2_VR_PWRGD

SVID JUMPERS

DDR_VTT_CTRL

DDR_VTT_PG_CTRL_BUF_OUT

VDD2_VR_FB_R

VDDQ_MEM_R

VDD2_VR_EN_DIO

VDD2_VR_EN_MUX

VDD2_VR_FB

VDD2_VR_EN

DDR_VTT_CTRL_BUF_IN

DDR_VTT_PG_CTRL

PM_SLP_S4_N

PWR : VDDQ_MEM/VDDQ_VTT

VDD2_VR_PHASE_LX

VDD2_VR_PHASE_SNUB

VDD2_VR_EN_S5

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

IN

74AUP1G07GW

A

NC

GND

Y

VCC

OUT

IN

IN

OUT

IN

IN

VIN2

CSD87330Q3D

BG

TG

VIN1

VSW
VSW

VSW

PGND

TGR

IN

OUT

rt8231agqw

EP

VTT

VLDOIN

BOOT

UGATE

PHASE

LGATE

PGND

CS

VDD

VID

PGOOD

TON

S5

S3

FB

VDDQ

VTTREF

GND

VTTSNS

VTTGND

OUT

OUT

tiger-html.html

MAX LOAD CURRENT: 3.7A

OUTPUT VOLTAGE: 2.5V

SW FREQ: 700KHZ

SOFT START: 227US

ISAT:5.0A

PWR : VDDQ_VPP

PCMB053T-4R7MS

CR-69 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE69

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 69 OF 80

INTEL CONFIDENTIAL
<>

2

1

L3J1

2

1

R3J1

2

1

R3J5

2

1

R3J3

1

2

CR3J1

2

1

R3J4

2

1

R3J2

2

1

R7W7

2

1

R7W6

2

1

C3J10

2

1

C3J12

2

1

R7W5

2

1

R7W4

2

1

R7W3

2

1

C7V11

2

1

C7W5

2

1

C7W4

2

1

C3J11

2

1

C7W2

2

1

C7W6

2

1

C3J2

2

1

C3J1

2

1

C7W3

2

1

C7W1

2

1

C7V12

2

16

15

14

13

1

12

11

10

9

3

17

8

7

5

4

6

EU7W1

69C3

69B8 68B8 79D4

69B5

69C3

69A3

69C5

68B8

79D4

69C7

16C7

64B3

79A7

60B7

65A1

68A8

77C6

16B6

64B3

79B7

60B7

65A4

71A7

71B1

75A3

75A8

75C3

75C8

77B8

78B2

69B5 69C3

VDDQ_VPP

VDD1_VPP_VR

V12_A

V3P3_A

IC

G58514-001

TPS54426

X5R

25V

20%

10UF

0603LF

X5R

10%

0.1UF

25V

0402LF

X5R

10%

0.22UF
0402LF

20%

47UF

6.3V

X5R
0603LF

25V

0402LF

X5R

10%

0.1UF

50V

0402LF

EMPTY

2200PF
10%

22PF
5%
COG
0402LF
50V

0402LF
25V

10%
X5R

0.1UF

0402LF

X5R

10%

1UF

25V

0402LF

1000PF

X7R

50V

10%

22UF
20%
X5R
0805LF
25V

5%

CH

0

0402LF

CH
0402LF

68.1K
1%

1/16W

0201LF
1/20W

1%
CH

30K

20%

47UF

X5R
0603LF
6.3V

1UF
10%
X5R
0402LF
25V

1/16W

0402LF

5%

1K

EMPTY

0402LF

CH

1/16W

1%

100K

5%

0402LF CH

330K

100 5%

CH

0402LF

DIO

SMLF

1N5819HW

D55839-001

5%

0402LF CH

0

0 5%

0402LF EMPTY

RESN

0805LF

0.005 1%

4.7UH

K80499-001

IND

VPP_VR_PHASE

VPP_VR_BST

VPP_VR_PWRGD

VPP_VR_FB

VPP_VR_PHASE

VPP_VR_BST_R

PWR : VDDQ_VPP

VPP_VR_EN

SVID JUMPERS

VPP_VR_PHASE_SNUB

VPP_VR_VREG5

VPP_VR_SS

VPP_VR_PWRGD

SLP_S3_S4_SEL

VPP_VR_EN

VPP_VR_EN_DIO

PM_SLP_S4_N

PM_SLP_S3_N

VPP_VR_PHASE

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

IN

IN

OUT

IN

OUT

IN

IN

POWERPAD

VO

VIN3

VIN2

VIN1

VBST

SW3

SW2

SW1

PGND2

PGND1

EN

PG

GND

SS
VREG5

VFB

tiger-html.html

ISAT:38A

20%

PLACE CA CLIOSE TO PIN18&19

PIN19 IS AGND, USE

MP2941B

SINGLE VIA AGND TO INNER GND

CA

VID TABLE

PWR : VCCIN_AUX

PLACE A GND VIA AS CLOSE AS
POSSIBLE TO PIN 4

MAX ISAT: 28.5A

SW FREQ: 1200KHZ

ITDC: 14A

ICCMAX: 27A

TPY OUTPUT VOLTAGE: 1.8V

PCH RAILS CONTROLLER

CR-70 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE70

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 70 OF 80

INTEL CONFIDENTIAL
<>

2

1

L6L1

2

1

R5M6

2

1

R5M3

2

1

R5M2

2

1

R5M5

2

1

R5M4

2

1

C5L3

2

1

R5L7

2

1

C5L2

2

1

R5L1

2

1

R5A1

2

1

R5L5

2

1

R5L4

2

1

C5L9

2

1

R5L8

2

1

R5M1

2

1

C5L1

2

1

R5L6

2

1

R5L2

2

1

R5L3

2

1

R5A2

2

1

C5L6

2

1

C5L7

2

1

C5L5

2

1

C5L8

2

1

C5L4

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

EU5L1

19B8

70B7

19B7

19B7

19B8

70A6

19B8

70A8

19B8

70B7

71B8 79C8

67B3 79C8

V1P8_A

V12_A

V3P3_A

V1P8_A

V3P3_A

VCCIN_AUX

VCCIN_AUX

K67720-001

IC

X5R
0805LF

10UF
10%

0805LF

10%

10UF

X5R

10%

10UF

0805LF

X5R

0805LF

X5R

10UF
10%

X5R

0.1UF

0402LF
25V

10%

150K 1%

EMPTY

0402LF

EMPTY

0402LF

150K 1%

0402LF CH

0

0

5%

5.1

0402LF
1/16W

CH

10%

1UF

6.3V

X5R
0402LF

0402LF

0

CH

0

0402LF CH

1%

2.2

0.22UF

X5R

10%

0402LF

0402LF CH

0

0

0

0402LF

0

CH

0402LF
1/16W

100
1%
CH

0402LF
1/16W

100

CH

1%

EMPTY

10V

0402LF

0.1UF 10%

1%

CH

0402LF

2.2

X5R

0402LF

10%

0.22UF

0402LF
1/16W

5%
CH

100K

1/16W

0402LF

100K
5%
CH

EMPTY

5%

100K

0402LF
1/16W

0402LF
1/16W

EMPTY

100K
5%

CH

1/16W

0402LF

5%

100K

0.22UH

IND

J42495-001

VCCIN_AUX_VSSSENSE_R

VCCIN_AUX_EN

SVID JUMPERS

VCCIN_AUX_CORE_VID0

PWR : VCCIN_AUX

VCCIN_AUX_VCCSENS

VR_PVCCIN_AUX_BST1_R

VCCIN_AUX_VCCSENSE_R

V3P3_VCCIN_AUX_VDD

VCCIN_AUX_VSSSENS

VCCIN_AUX_CORE_VID1
VCCIN_AUX_CORE_VID0

VR_PVCCIN_AUX_BST2
VR_PVCCIN_AUX_BST1

VCCIN_AUX_CLM

VCCIN_AUX_MODE

VCCIN_AUX_CORE_VID1

VCCIN_AUX_FS

VCCIN_AUX_VR_PWRGD

VR_PVCCIN_AUX_BST2_R

VCCIN_AUX_PHASE_NODE

V1P8A_PWRGD

CAD NOTE:

CAD NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

BI

MP2941B

AGND

3V3

RGND

VOUT

MODE

CLM

BST1

SW1

SW2

BST2

PG

EN

FS

VID0

VID1

PGND

PGND

VIN

PGND

OUT

OUT

OUT

IN

IN

IN

tiger-html.html

ISAT:2.2A

OUTPUT VOLTAGE: 0.78V

VNN_EXT

VID1:0 - 0.70V
VID1:1 - 0.76V

PWR : VNN/V1P05_A BYPASS

VID2:1 - 0.96V

VID2:0 - 1.05V

V1P05_EXT

MAX LOAD CURRENT: 0.5A

VNN_EXT

ISAT:1A

0.5A

0.5A

V1P05_EXT

OUTPUT VOLTAGE: 1.05V

SOFT START: 1.5MS

MAX LOAD CURRENT: 0.5A

SOFT START: 1.5MS

SW FREQ: 800KHZ

SW FREQ: 800KHZ

CR-71 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE71

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 71 OF 80

INTEL CONFIDENTIAL
<>

2

1

C2D7

2

1

C3D1

2

1

R3C6

2

1

R2D7

2

1

R3D2

2

1

R2D10

2

1

C7N1

4

5

3

2

1

U7N1

2

1

R7N2

2

1

R7N1

2

1

R2C6

2

1

R3D5

2

1

R2C10

2

1

R2C7

2

1

C3C7

2

1

C3C6

2

1

R2D1

2

1

C2C10

2

1

L2C1

2

1

L2D1

2

1

R2D2

2

1

C2D8

2

1

C2E1

2

1

3

Q2E1

2

1

R2E2

2

1

3

Q2D1

2

1

C3D2

2

1

C3C5

2

1

C3D4

2

1

C3D3

2

1

C2D10

2

1

C2C9

2

1

R2C8

2

1

R2D9

2

1

R2D4

2

1

R2D8

2

1

C2D4

2

1

C2D6

2

1

C2D5

2

1

C2D3

2

1

C2D1

2

1

C2D2

2

1

C2C8

2

1

R2D11

2

1

R2D6

2

1

R2C11

2

1

R2D3

2

1

R2C9

2

1

R2D5

5
16

10
11

14
13

8

7

12
9

4

1

6

15

3

2

17

U2D1

19B8

19B8

70B3

79C8

79C8

71C4

16B6 64B3
79B7 60B7

65A4 69A7

71A7 75A3

75A8 75C3

75C8 77B8

78B2

71A3
71C3

16B6

64B3

79B7

60B7

65A4

69A7

71B1

75A3

75A8

75C3

75C8

77B8

78B2

71C4

71A3

71C8

V3P3_A

V5_A

V12_A

VNN_EXT_OUT

V3P3_A

VNN_EXT

V1P05A_EXT_OUT

V1P05_EXT

V3P3_A

V3P3_A

K76542-001

IC

APW8743

EMPTY
0402LF

1%

1/16W

10K

0402LF

EMPTY

1/16W

100K
5%

5%

1K

1/16W

EMPTY
0402LF

5%

1/16W

EMPTY

1K

0402LF

0

CH

0402LF

0

0402LF CH

0 0

X5R
0402LF

10UF

10V

20%

0603LF
25V

10UF
20%
X5R

0603LF

10UF
20%
X5R

25V

0402LF
25V

0.1UF
10%
X5R

25V

10UF
20%
X5R
0603LF

25V

0603LF

10UF
20%
X5R

0402LF

X5R

25V

10%

0.1UF

0402LF
1/16W

10K
1%
CH

1%

0402LF
1/16W

EMPTY

10K

0402LF
1/16W

CH

10K
1%

0402LF

10K 1%

CH

10V

1UF

X5R

20%

0402LF

1UF

10V

0402LF

20%
EMPTY

6.3V

0603LF

X5R

20%

22UF

6.3V

0603LF

X5R

20%

22UF

6.3V

X5R
0603LF

20%

22UF

10%

25V

0.1UF

X5R
0402LF

J56149-001

MOSFET

0402LF

CH

100K

1/16W

5%

J56149-001

MOSFET

10%
X7R
0402LF

10NF

16V

10%

0.1UF

X5R

0402LF

25V

0402LF

0

0

CH

30%

1UH

2.2A

INDUCTOR

J49688-001

J51059-001

10UH

INDUCTOR

20%

1A

25V

X5R

0402LF

0.1UF 10%

0402LF CH

0

0

6.3V

22UF
20%
X5R
0603LF

0402LF

10%

0.1UF

25V

X5R

0402LF
1/16W

5%

0

CH

1/16W

EMPTY
0402LF

0
5%

0

CH

0603LF

1A

0805LF

1%

0.005

RESN

0402LF

0 0

EMPTY

0

CH

0

0402LF

IC
C78568-001

X5R

25V

0402LF

0.1UF
10%

0
5%

1/16W

0402LF

EMPTY

0

1/16W

CH
0402LF

5%

0402LF
1/16W

EMPTY

0
5%

0603LF CH

0 1A

2200PF
10%
EMPTY
0402LF
50V

EMPTY

2200PF
10%

0402LF
50V

V1P05A_EXT_BYPASS_VID

VNN_EXT_VID_R

VNN_CTRL

SVID JUMPERS

PWR : VNN/V1P05_A BYPASS

V1P05_CTRL

VCCIN_AUX_VR_PWRGD

VNN_V1P05A_PWRGD

VNN_EXT_BST

V1P05A_EXT_VOUT

VCCIN_AUX_VR_PWRGD_EN2

PM_SLP_S3_N

VNN_SLP_S3

V1P05A_EXT_VOUT
VNN_EXT_VOUT

PM_SLP_S3_N

VNN_EXT_VOUT

VNN_EXT_OUT_J

V1P05A_EXT_BST

VNN_EXT_BYPASS_VID

VCCIN_AUX_VR_PWRGD_EN1

VNN_EXT_BST_R

V1P05A_EXT_BST_R

VNN_EXT_BYPASS_VID

VNN_EXT_PHASE

V1P05A_EXT_PHASE

VNN_SNUB

V1P05A_SNUB

VCC_VNN_V1P05A_EXT

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

IN

D

S

G

D

S

G

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

G

74AHC1G08

V

AGND_TPD

PGND_2
PGND_1

VOUT1

LX1

BOOT1

VIN1

VIN2

BOOT2

LX2

VOUT2

POK

VID1

VID2

EN1
EN2

VCC

tiger-html.html

SW FREQ: 800KHZ

MAX IRMS: 40A

IPL2: 43A

RA

CONTROLLER PMBUS

TYP OUTPUT VOLTAGE: 1.89V

CPU RAILS IMVP 9 CONTROLLER

PWR : VCCIN

ICCMAX: 65A

RA - 825OHM FOR DC_LL=2MOHM

PLACE CLOSE TO DEVICE

FOR DEBUG & PROGRAMMING ONLY

MAX ISAT: 50A

MP2940AGRT-011E

I2C - 0X20H

CR-72 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE72

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 72 OF 80

INTEL CONFIDENTIAL
<>

2

1

R9F5

2

1

R9F6

2

1

R1T5

2

1

R1T6

2

1

R9F4

2

1

R1T7

2

1

R9F10

2

1

R1T1

2

1

R9F3

2

1

R1T3

15

16

6
7

28

5

4

25
11

26

19

13

17

12

18

22
23
24

27

20

10

9

21

8

1
2
3

14

29

EU9F1

2

1

R9G10

2

1

R9F14

2

1

C9F3

2

1

R9G8

2

1

R9G4

2

1

R9G7

2

1

R9F12

2

1

R9G3

2

1

R9G6

2

1

C9G2

2

1

R9F1

2

1

R9F7

2

1

R1T4

2

1

C9F1

2

1

R9F2

2

1

R1T2

2

1

C9G1

2

1

R9G1

2

1

R9F16

2

1

R9G2

2

1

C9F5

2

1

C9F4

2

1

R9G5

2

1

C9G3

2

1

R9F17

2

1

C9F2

2

1

C9F6

2

1

R9F15

2

1

R9F13

72B3

73A2

74A2

11C1

74B3

17B6
17A6

22C6 22D7 72B2

22C6

22D7

72A3

72C6

72C6

78C1

72B6

68B6

68D8

79D4

73A5 74A5

73B4
74B3

72B6

11C1

74B6
73B6

17B1

79C3

72D1

72D1

72A8 73A2 74A2

72A6

72A1

17A1

17C1

73B4

VCCIN

V12_A

V3P3_A

V3P3_A

V3P3_A

VCCSTG_TERM

V3P3_A

V3P3_A

0603LF

61.9K

1/16W

CH

1%

0402LF
1/16W

CH

59K
1%

16V

5%
COG
0402LF

330PF

4.7UF

0402LF
6.3V

X5R

20%

0

0402LF
1/20W

0
CH

10%

10V

0402LF

EMPTY

0.1UF

EMPTY

0402LF

0

0

6.3V

10%
X5R
0402LF

1UF

16V

EMPTY

10%

0402LF

10NF

CH

1%

825

0402LF

RESN
0402LF
1/16W

1%

133K

0402LF

RESN

1%

2M

1/16W

0402LF

10NF

50V

X7R

10%

0

CH

0402LF

0

0

0

0402LF EMPTY

10%

0.1UF

10V

0402LF

EMPTY

0

0

0402LF CH

1%

10K

EMPTY
0402LF
1/16W

0

0

0402LF CH

0.1UF

0402LF

10V

10%

EMPTY

0402LF CH

1%

1.5K

CH

0402LF

1%

1.5K

1/16W

CH

49.9K

0402LF

1%

CH

0 0

0402LF

0402LF

0 0

CH

1/16W

0402LF

CH

1%

100

10%

6.3V

1UF

0402LF

X5R

0402LF

0

CH

0

1%

0402LF
1/16W

100

CH

K74151-001

MP2940A

IC

1/16W

EMPTY
0402LF

1%

10K

10K

CH

5%

0402LF
1/16W

0402LF
1/16W

EMPTY

10K
1%

5%
RESN

1/10W

4.7

0402LF

0402LF

1%

1/16W

EMPTY

10K

0402LF

1%

10K

EMPTY

1/16W

1%

0402LF

EMPTY

10K

1/16W

10K
1%
EMPTY
0402LF
1/16W

0

0

EMPTY

0402LF

EMPTY

0 0

0402LF

IMVP9_VDIFF_VFB_R

IMVP9_VDIFF

VCCIN_VR_SYNC

GPPC_B10_I2C5_SCL

VCCIN_CS2

VCC_VCCIN_SENSE_P
VCC_VCCIN_SENSE_N

H_PROCHOT_N

H_PROCHOT_N

VCCIN_SCL_P

VCCIN_SDA_P

PWR : VCCIN

ALL_SYS_PWRGD

VCCIN_CS_SUM

IMVP9_VR_EN

VDD2_VR_PWRGD

VCCIN_PH_FAULT_N

VCCIN_VR_TEMP

VCCIN_VR_PE

GPPC_B9_I2C5_SDA

VCCIN_PWM2
VCCIN_PWM1

IMVP9_VFB

VCCIN_VOSEN
VCCIN_VORTN

IMVP9_IMON

IMVP9_IREF

V1P8_IMVP9_VDD

VR_SVID_ALERT_N

IMVP9_VR_READY

VCCIN_SDA_P
VCCIN_SCL_P

VCCIN_VR_SYNC

VCCIN_VR_PE

IMVP9_VR_EN

V3P3_IMVP9_VDD

VCCIN_VR_TEMP_R

CHGR_PSYS_IMVP

V12_IMVP9_VIN

IMVP9_PROCHOT_N

VR_SVID_CLK
VR_SVID_DATA

VCCIN_CS1

DESIGN NOTE:

DESIGN NOTE:

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

BI

BI

OUT

OUT

OUT

SDIO

SCLK

AGND_TPD

CSSUM

VRHOT_N

VIN_SEN

PSYS

TEMP

VDD33

EN
PE

STB

SCL_P

SDA_P

VRRDY

ALT#

VDD18

IREF
IMON

VORTN

VOSEN

VFB

VDIFF

CS1

CS2

CS3

PWM1

PWM2

PWM3

IN
IN

IN

OUT
OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

BI

IN

BI

IN

OUT

IN
IN

BI

BI

tiger-html.html

WITH A MINIMUM OF 40 VIAS

VCCIN IS CONNECT TO THE PGND PLANE

VCCIN POWER CONVERSION PHASE I

ISAT:38A

CR-73 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE73

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 73 OF 80

INTEL CONFIDENTIAL
<>

2

1

L3T2

2

1

R2U4

2

1

R2U3

2

1

R2U9

2

1

R2U1

2

1

R2U2

2

1

C7F4

2

1

C7F3

2

1

R2T9

2

1

C2T8

2

1

C2U4

2

1

R2U6

2

1

C2U7

2

1

C2U5

2

1

C2U2

2

1

C2U3

2

1

C2U1

2

1

C8G1

2

1

C8G2

2

1

C2U6

2

1

R2U5

18

14

2

22
20

19

4
3

15

13
5

23

16

17

1

21

U2U1

72C3

74B3 72B1

73A8

72A8 72B3 74A2

73A4

73B6

72B3

73B4

74A5 72A1

V3P3_A

V3P3_A

VCCIN

V12_A

IC

MP86909GR

J84022-001

CH

0

0

0402LF

10%

0402LF
10V

X5R

1UF

X5R

10%

25V

0402LF

1UF

25V

0402LF

X5R

10%

0.1UF

X5R
0805LF

20%

25V

22UF

25V

22UF

X5R

20%

0805LF

20%

22UF

0805LF

X5R

25V

25V

TANT

22UF

20%

3528LF

1UF

10V

0402LF

X5R

10%

2.2

0402LF CH

1%

0402LF

10V

10%

0.22UF

X5R

10%

50V

EMPTY
0402LF

3300PF

5%

EMPTY

1K

0402LF

X7R
0805LF

10%

6.3V

10UF

6.3V

X7R

10UF
10%

0805LF

CH

0402LF

0 0

0 0

EMPTY

0402LF

CH

0

0402LF

0

CH

0402LF

10K 1%

10K

0402LF

1%

CH

J42495-001

IND

0.22UH

VCCIN_CS1

VCCIN_VR_TEMP

VCCIN_PH1_NC1

V3P3A_VCCIN_VDD_PH1

VCCIN_SYNC_PWM1_EN

VCCIN_VR_SYNC

VCCIN_PH1_NC2

VCCIN_PH1_NC2

VCCIN_PH1_SNUB

VCCIN_PH1_PHASE

VCCIN_PH1_BST

VCCIN_PWM1

PWR : VCCIN PH1

SVID JUMPERS

V3P3A_VCCIN_VDRV_PH1

VCCIN_PH1_NC1

VCCIN_PH_FAULT_N

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

PGND

FAULT#

VDRV

AGND

VDD

SYNC

VTEMP

CS

EN

PWM

VIN

PGND

SW
SW

VIN

BST

tiger-html.html

VCCIN IS CONNECT TO THE PGND PLANE
WITH A MINIMUM OF 40 VIAS

VCCIN POWER CONVERSION PHASE II

ISAT:38A

CR-74 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE74

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 74 OF 80

INTEL CONFIDENTIAL
<>

2

1

L3T1

2

1

R2T5

2

1

C2T4

18

14

2

22
20

19

4
3

15

13
5

23

16

17

1

21

U2T1

2

1

C2R2

2

1

C7F1

2

1

R2T1

2

1

C2T3

2

1

C7F2

2

1

C2T7

2

1

R2T8

2

1

R2T4

2

1

C2T6

2

1

R2T7

2

1

R2T6

2

1

C2T5

2

1

C2T2

2

1

C2T1

2

1

C8F2

2

1

C8F1

2

1

R2T3

2

1

R2T2

72A8 72B3 73A2

74B6

74A4

72B3

74B3

74A8

72C3

73B4 72B1

73A5 72A1

V3P3_A

V12_A

V3P3_A

VCCIN

0

0402LF EMPTY

0

0

CH

0

0402LF

0.1UF
10%

0402LF

X5R

25V

X5R

10%

0402LF
25V

1UF

0805LF

X5R

22UF
20%

25V

0805LF

20%

22UF

X5R

25V

25V

3528LF

22UF

20%

TANT

CH

0402LF

2.2 1%

0402LF CH

0

0

10%

10V

0402LF

1UF

X5R

CH

0402LF

1%

10K

0402LF

0

0

CH

1UF
10%

0402LF

X5R

10V

0805LF

X7R

10%

10UF

6.3V

X5R

10%

0.22UF

10V

0402LF

5%

1K

0402LF EMPTY

10UF

6.3V

0805LF

10%
X7R

0402LF

EMPTY

10%

3300PF

50V

MP86909GR

IC

J84022-001

25V

X5R

22UF

0805LF

20%

0402LF CH

10K 1%

J42495-001

IND

0.22UH

VCCIN_PH2_PHASE

VCCIN_SYNC_PWM2_EN

VCCIN_VR_SYNC

VCCIN_PH2_NC2

VCCIN_PH2_NC2

VCCIN_PWM2

V3P3A_VCCIN_VDD_PH2

VCCIN_PH2_NC1

VCCIN_PH2_SNUB

V3P3A_VCCIN_VDRV_PH2

VCCIN_PH2_NC1

VCCIN_PH2_BST

VCCIN_CS2

SVID JUMPERS

VCCIN_VR_TEMP

PWR : VCCIN PH2

VCCIN_PH_FAULT_N

CAD NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

PGND

FAULT#

VDRV

AGND

VDD

SYNC

VTEMP

CS

EN

PWM

VIN

PGND

SW
SW

VIN

BST

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

IN

tiger-html.html

V5_S RAIL GENERATION

V12_S POWER GENERATION

4A

PWR : S0 RAILS

V3P3_S POWER GENERATION

4A

6A

2.5A

V1P8_S POWER GENERATION

CR-75 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE75

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 75 OF 80

INTEL CONFIDENTIAL
<>

1

5

2

8

3

7

U1E1

3

2

1

4

5

Q7V1

2

1

R9G9

1

5

2

8

3

7

U9T1

2

1

C9T1

2

1

C9T3

2

1

C9T2

2

1

C8V3

2

1

3

Q8W1

2

1

R7W2

2

1

C8W6

2

1

R8W6

2

1

C1F1

2

1

C1E8

2

1

C1E7

2

1

C1F2

2

1

C9G4

2

1

C9G6

2

1

C9G5

1

5

2

8

3

7

U9G1

16B6

64B3

79B7

60B7

65A4

69A7

71A7

71B1

75A3

75A8

75C3

77B8

78B2

16B6

64B3

79B7

60B7

65A4

69A7

71A7

71B1

75A3

75C3

75C8

77B8

78B2

16B6

64B3

79B7

60B7

65A4

69A7

71A7

71B1

75A8

75C3

75C8

77B8

78B2

16B6

64B3

79B7

60B7

65A4

69A7

71A7

71B1

75A3

75A8

75C8

77B8

78B2

V3P3_A

V5_A

V5_S

V3P3_S

V12_A

V12_S

V5_A

V3P3_A

V3P3_A

V1P8_S

V1P8_A

K36991-001

IC

25V

X5R

10%

0.1UF

0402LF

0402LF
10V

20%
X5R

10UF

X7R

10%

0402LF

2200PF

50V

0402LF

X7R

10%

2200PF

50V

0.1UF

X5R
0402LF
25V

10%

X5R

20%

6.3V

10UF

0402LF

10%

25V

0.1UF

X5R
0402LF

CH

1%

0402LF

10K

0402LF
10V

X5R

10%

1UF

CH

1%

1/16W

0402LF

10K

MOSFET

C81974-001

10UF
20%
X5R
1206LF
25V

X7R

10%

2200PF

50V

0402LF

10%

0.1UF

X5R
0402LF
25V

20%

10UF

10V

X5R
0402LF

IC

K36991-001

1A

0

0603LF CH

E75612-001

MOSFET

K36992-001

REV=1

1OF1

IC

V12S_PWR_EN

V12S_PWR_DIS

PM_SLP_S3_N

PM_SLP_S3_N

PM_SLP_S3_N

V1P8S_SR_CAP

V5S_SR_CAP

PM_SLP_S3_N

V3P3S_LS

V3P3S_SR_CAP

SVID JUMPERS

PWR : V12_S/V5_S/V3P3_S/V1P8_S

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

SLG5NT1765VTR

GND

CAP

S

D

ON

VDD

MOSFET_P_SING

8
7
6

SLG5NT1502VTR

S

D

ON

VDD

GND

CAP

IN

SLG5NT1502VTR

S

D

ON

VDD

GND

CAP

D

S

G

IN

IN

IN

tiger-html.html

V3P3_A_LAN POWER GENERATION

4A

PWR : LAN RAILS

CR-76 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE76

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 76 OF 80

INTEL CONFIDENTIAL
<>

2

1

R8D3

2

1

R8D6

1

5

2

8

3

7

U8D2

2

1

R8D4

2

1

C8D11

2

1

C8D16

2

1

C8D12

11C1

V3P3_A

V3P3_A

V3P3_A

V3P3_A_LAN

10%

0402LF

X5R

0.1UF

25V

0402LF

2200PF
10%
X7R

50V

10UF

10V

X5R

20%

0402LF

CH

0402LF

5%

0

K36991-001

IC

1A

0

CH

0603LF

0603LF

1A

EMPTY

0

GPPC_B8_V3P3_LAN_EN

V3P3_LAN_EN

PWR : LAN RAIL

V3P3M_LS

V3P3M_LAN_CAP_SR

SVID JUMPERS

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

IN

SLG5NT1502VTR

S

D

ON

VDD

GND

CAP

tiger-html.html

PWR : VCCSTG

SOFT START : 51.2US

PWR : VCCST

SOFT START : 33.8US

CR-77 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE77

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 77 OF 80

INTEL CONFIDENTIAL
<>

2

1

R5C6

2

1

C5B13

8

3

1

16

2

15
13

14

U5C1

2

1

C5C3

2

1

C5C2

2

1

R5B2

2

1

R5B1

2

1

C5C1

4

6

5

3

1

2

U5B1

2

1

R5C2

2

1

R5C1

2

1

R5N2

2

1

R5N3

4

5

3

Q5N1

2

1

R5N1

1

2

6

Q5N1

2

1

R5M8

2

1

C5N2

2

1

C5N1

2

1

R5N6

2

1

C5N4

8

3

1

16

2

15
13

14

U5N1

2

1

R5M7

2

1

R5M9

2

1

C5M1

4

6

5

3

1

2

U5M1

16B6

64B3

79B7

60B7

65A4

69A7

71A7

71B1

75A3

75A8

75C3

75C8

78B2

77D1

77A7

16C7

79A7

40A3

77D1

77B8

16A2

16C2

77A7 77B8

16C7

64B3

79A7

60B7

65A1

68A8

69A7

V3P3_A

VCCSTG

V5_A

V1P05_OUT_FET

V1P05_OUT_FET

V1P05_OUT_FET

V1P05_OUT_FET

V3P3_A

VCCSTG

VCCST

V5_A

V3P3_A

VCCST

IC

G59945-001

SN74AUP1G32

0402LF
10V

0.1UF

X5R

10%

5%

0

0402LF CH

5%

0402LF EMPTY

100K

J99037-001

IC

SLG5NT1757VTR

X5R

10UF

6.3V

0603LF

20%

1%

EMPTY

0805LF

0.01

16V

X7R
0402LF

0.1UF
10%

X5R

50V

10%

3300PF

0402LF

5%

0

1/16W

0402LF

EMPTY

MOSFET

D52888-001

BSS138DW

1/16W

0402LF

CH

5%

100K

BSS138DW

D52888-001

MOSFET

5%
CH

100K

1/16W

0402LF

100K

1/16W

0402LF

CH

5%

0 5%

CH

0402LF

0402LF

0 5%

EMPTY

IC

SN74AUP1G32

G59945-001

0.1UF
10%
X5R

10V

0402LF

5%

0

CH

0402LF

0
5%
EMPTY

1/16W

0402LF

50V

10%

4700PF

X7R
0402LF

10UF
20%
X5R

6.3V

0603LF

IC

J99037-001

SLG5NT1757VTR

0.1UF
10%

16V

X7R
0402LF

0.01

0805LF

1%

EMPTY

PM_SLP_S3_N

V3P3_VCCST_OVERRIDE

VCCST_LS_SLEW_CAP

VCCST_EN

VCCST_SLPS3_OUT

VCCST_OVERRIDE_EN_N

PM_SLP_S0_N

VCCSTG_EN

V3P3_VCCST_OVERRIDE

SLP_S0_C10_GATE_N

VCCSTG_C10_OUT

VCCST_OVERRIDE_R

PWR : VCCST/VCCSTG

CPU_C10_GATE_N

VCCSTG_LS_SLEW_CAP

V3P3_VCCST_OVERRIDE

PM_SLP_S4_N

SVID JUMPERS

DESIGN NOTE:

DESIGN NOTE:

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

ON

GND

CAP

GND

VOUT

VIN

NC

VDD

VCC

Y

NC

A

GND

B

IN

IN

IN

IN

OUT

G

FET_N_DUAL

S

D

G

FET_N_DUAL

S

D

IN

ON

GND

CAP

GND

VOUT

VIN

NC

VDD

IN

IN

VCC

Y

NC

A

GND

B

tiger-html.html

PWR : SEQUENCE LOGIC I

SLG7NT43590

VOLTAGE SENSE

CR-78 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE78

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 78 OF 80

INTEL CONFIDENTIAL
<>

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

U2F1

2

1

R2F17

2

1

R2F15

2

1

R2F13

2

1

R2F14

2

1

R2F16

2

1

R1G2

2

1

R1F11

2

1

CR2F1

2

1

CR2F2

2

1

R2F3

2

1

R1F8

2

1

R1F6

2

1

C1F5

2

1

R1F3

2

1

R1F1

2

1

C1F3

2

1

R1F7

2

1

C1F4

2

1

R1F5

2

1

R2F9

2

1

C2F1

2

1

R2F4

2

1

R2F18

2

1

R2F8

2

1

R2F20

2

1

R1G1

2

1

R2G6

2

1

R1F4

2

1

R1G3

2

1

R1F10

2

1

R2F22

2

1

R2F10

2

1

R1F9

2

1

R1F2

2

1

C2F2

2

1

R2F25

78C1

78C1

16A8

78D6

78A4
78A5
78A2

60A3

60B7

78C8

60A3

60B7

78B8

78C8

16B6 64B3 79B7 60B7 65A4 69A7 71A7 71B1
75A3 75A8 75C3 75C8 77B8

78B8

78B5 79C1 16C7

60A3 60B8

79D1

78A7

65B3

79C5

16B5

78C1

79C1

16C7

66C3

67B8

79D8

78B5 16A8
72A4

79B8

79A1 79C5 79B4

78C8

78C8

78C8

78C1

78C8

16C7 79C3

78B8

V12_A

V3P3_A

V3P3_S

V3P3_S

V3P3_A

V3P3_A

V1P8_S

VCCST

5%
CH

0

0402LF
1/16W

X5R

0.47UF

10V

0402LF

10%

CH

5%

0

0402LF

CH

0402LF

0 5%

0402LF

0 5%

CH

5%

0

CH

0402LF

0402LF

0 5%

CH

1%

100K

CH

1/16W

0402LF

0402LF

1%

100K

1/16W

CH

0402LF

CH

1/16W

100K
1%

100K
1%
EMPTY
0402LF
1/16W

100K
1%
CH
0402LF
1/16W

1/16W

0402LF

CH

100K
1%

0

0402LF

5%

CH

0402LF

1%

1/16W

51.1K

CH

25V

0.1UF

X5R
0402LF

10%

1%

68.1K

0402LF
1/16W

CH

150K
1%
CH

1/16W

0402LF

0.1UF

X5R
0402LF

10%

25V

CH

1/16W

0402LF

68.1K
1%

10%

0.1UF

0402LF

X5R

25V

1%

68.1K

CH

1/16W

0402LF

1%

0402LF
1/16W

EMPTY

68.1K

0402LF

COG

47PF
5%

50V

RESN

316K

1/10W

0402LF

1%

5%

30K

0402LF
1/16W

CH

CH

100 5%

0402LF

30V

100MA

DIO

H34213-001

DIO

100MA

30V

0 5%

0402LF EMPTY

100K

CH

0402LF

1%

CH

0 5%

0402LF

0402LF
1/16W

100K
1%
CH

0 5%

0402LF EMPTY

5%

0402LF CH

0

EMPTY

5%

0

0402LF

IC

K76641-001

SYS_PG_SLG_OUT

RSMRST_PG_SLG_OUT
DPWROK_SILEGO_OUTPUT

VCCST_PG_SLG_OUT

H_VCCST_PWRGD

V3P3A_DSW_PWRGD

SLG7NT43590_VDD

V3P3S_SENSE
VCCST_CPU_SENSE
V1P8S_SENSE

SIO_PWROK

SIO_PWROK

VCCST_CPU_SENSE

PM_SLP_S3_N

SIO_SYS_PWROK

PCH_PWROK

SLG_PWRBTN_SIO_IN

SIO_PWROK_R

PCH_PG_SLG_OUT

PWRGD_DDR_VRS

ALL_SYS_PG_SLG_OUT

V12A_SENSE

VCCST_CPU_SENSE_R

FP_PWRBTN_N

PWRGD_SUS_VRS

SLG_PWRBTN_N

PCH_PWROK

V5A_V3P3A_VR_PWRGD

VCCST_PWRGD_PCH_PWROK_DIS

H_VCCST_PWRGD
ALL_SYS_PWRGD

PCH_DPWROK

RSMRST_PWRGD_N

V3P3S_SENSE

PWR : SEQUENCE I

V1P8S_SENSE

V12A_SENSE

SIO_SYS_PWROK

V3P3A_DSW_PWRGD

SYS_PWROK

SYS_PG_SLG_OUT

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

PWRBTN_SIO_IN

SLG_SYS_PWROK

SYS_PWROK

SIO_PWROK

PCH_PWROK

DDR_VCCIO_PWRGD

ALL_SYS_PWRGD

V3P3A_DSW_PWRGD

RSMRST_PWRGD_N

VBAT_MON

V3

GND

V2

PWRBTN_DSW_N

VCCST_PWRGD

PWRBTN_N

V1

SUS_VR_PWRGD

DPWROK

VDD

IN

OUT

IN

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

tiger-html.html

PWR : SEQUENCE LOGIC II-PWRGD

DDR_VR PWRGOOD

SUS_VR PWRGOOD

DSW PWROK

TRIPAD

PCH GLITCH MITIGATION

PCH PWROK

RSMRST_PWRGD

CR-79 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE79

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 79 OF 80

INTEL CONFIDENTIAL
<>

2

1

R6T4

2

1

R2G10

2

1

R5C3

2

1

R6R9

2

1

R3F8

2

1

R1R1

2

1

R6R15

2

1

R6T1

2

1

R2G1

2

1

R2G4

2

1

R2G8

2

1

CR2G1

2

1

R2G9

2

1

3

Q2F1

2

1

R2F1

2

1

R2E3

2

1

R2F2

2

1

R2G11

2

1

R2G5

2

1

R2F27

2

1

R2F26

1

2

CR2F3

2

1

R2F7

2

1

R2F6

2

1

R2F5

2

1

R2F12

2

1

R2F11

2

1

R2G7

2

1

R2G3

2

1

R2F19

2

1

R2G2

2

1

R2F21

2

1

C2F3

16C7 64B3
60B7 65A1

68A8 69A7

77C6

78C1 79C5 79B4

78B6

16C7

78C8

69B8

69C5

68B8

78B5 78C1 16C7

72B2

78C1

16C7

70B3

71B8

66C3

67B8

78D8

67B3

70B3

71B8

78C8

16A1 64B3 39B7 40C5 47A4 48A4 50C7
52A8 57A7 60A8 63A7

16B6 64B3
60B7 65A4

69A7 71A7

71B1 75A3

75A8 75C3

75C8 77B8
78B2

79B1

16C7

38A4

21A4

16C7 40A3
77A8

16C7 60B7 66A8 67C8 79C8

16C7

16C7 65A1

78C1 79A1 79B4

16C7

79A5

60B7

66A8

67C8

68B6

68D8

72A4

16C7 38A4 79B8

78C1

79A1

79C5

60A3

60B7

V3P3_A

V3P3_A

V3P3_S

V3P3_A

V3P3_A

EMPTY

0.01UF

0402LF

10%

50V

CH

0402LF

0 5%

0402LF

5%

EMPTY

0

1M

0402LF
1/16W

CH

5%

CH

5%

0

0402LF

0

0402LF

5%

EMPTY

1/16W

0402LF

CH

1%

100K

10K

0402LF CH

1%

0402LF

10K

EMPTY

1%

10K 1%

EMPTY

0402LF

1%

0402LF CH

10K

1N5819HW

SMLF

DIO

EMPTY

5%

0

0402LF

0402LF

1%

100K

1/16W

EMPTY

10K 1%

EMPTY

0402LF

0402LF

10K 1%

CH

5%

0201LF CH

0

1/16W

0402LF

5%

10K

EMPTY

0402LF

CH

10K

1/16W

5%

MOSFET

C81974-001

0402LF
1/16W

10K
5%
CH

H34213-001

DIO

100MA

30V

0402LF
1/16W

10K
1%
EMPTY

1/16W

100K

CH
0402LF

1%

CH

5%

0402LF

0

1/20W

CH
0201LF

100K
1%

0201LF

100K
1%

1/20W

CH

0201LF

CH

1/20W

100K
1%

0201LF

100K

CH

1%

1/20W

1%

1/20W

0201LF

CH

100K

CH

1/20W

0201LF

100K
1%

5%

CH

0402LF

1K

1%

0201LF

CH

100K

1/20W

PM_SLP_S4_N

RSMRST_PWRGD_N

SYS_PWROK

PWRGD_DDR_VRS

VPP_VR_PWRGD

PCH_PWROK

IMVP9_VR_READY

PCH_DPWROK

DSW_PWROK

VCCIN_AUX_VR_PWRGD

V5A_V3P3A_VR_PWRGD

V1P8A_PWRGD

VNN_V1P05A_PWRGD

PWRGD_SUS_VRS

PM_PLTRST_N

PM_SLP_S3_N

RSMRST_N

SKTOCC_N

SKTOCC_R_N

PWR : SEQUENCE II/GLITCH FREE

PM_SLP_S0_N

PM_SLP_SUS_N

PM_SLP_LAN_N

PM_SLP_S5_N

RSMRST_PWRGD_N

PM_SLP_SUS_N

VDD2_VR_PWRGD

RSMRST_N_R

RSMRST_N

RSMRST_PWRGD_N

SIO_RSMRST_N

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3

CAD NOTE:

OUT

OUT

OUT

OUT

OUT

IN

OUT

D

S

G

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

tiger-html.html

CHANGELOG

CR-80 : @TIGER_ISLAND_LIB.TGI(SCH_1):PAGE80

TIGER ISLAND

K56089-100

TIGER LAKE ULT

1.00

SHEET 80 OF 80

INTEL CONFIDENTIAL
<>

CHANGELOG

INTEL CORPORATION

REV:

DOCUMENT NUMBER:

TITLE:

7

1

D

D

2

1

3

4

5

8

A

B

6

7

A

4

5

C

B

C

8

2

6

3