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IEEE Microwave and Guided Wave Letters
Volume 10 Number 2, February 2000

On-Chip Interconnect Lines with Patterned Ground Shields

Page 49.

Abstract:

Measurements of on-chip interconnect lines with a patterned ground shield (PGS) are analyzed and compared to lines with no ground shield (NGS). At frequencies at and below 7 GHz, the PGS lines have about one fifth the dissipative loss of that of the NGS lines. By using a doped layer in the silicon for the shield, as opposed to other metal layers which are closer to the line,a reasonably high characteristic impedance is maintained. The transmission line characteristics are also analyzed.

References

1. S. Seki and H. Hasegawa, "Cross-tie slow-wave coplanar waveguide on semi-insulating GaAs substrates", Electron. Lett., vol. 17, no. 25, p.  940,  Dec.  1981.
2. T. Wang and T. Itoh, "Compact grating structure for application to filters and resonators in monolithic microwave integrated circuits", IEEE Trans. Microwave Theory Tech., vol. MTT-35, p.  1176, Dec.  1987.
3. R. Lowther, "Integrated circuit with an improved inductor structure and method of fabrication", U.S. Patent 5 717 243, Filed Apr. 24, 1996, issued Feb. 10, 1998.
4. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields For Si-based RF IC's", IEEE J. Solid State Circuits, vol. 33, p.  743,  May  1998.
5. Y. Eo and W. R. Eisenstadt, "S-parameter-based IC interconnect transmission line characterization", IEEE Trans. Comp. Hybrids, Manuf. Technol., vol. 15, p.  555, Aug.  1992.