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MAKE Macros
Syntax | Default MAKE Macros | Modifying Default MAKE Macros | See Also
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A macro is a variable that MAKE expands into a string whenever MAKE encounters the macro in a makefile. For example, you can define a macro called LIBNAME that represents the string "mylib.lib." To do this, type the line LIBNAME = mylib.lib at the beginning of your makefile. Then, when MAKE encounters the macro $(LIBNAME), it substitutes the string mylib.lib. Macros let you create template makefiles that you can change to suit different projects.

To use a macro in a makefile, type $(MacroName) where MacroName is a defined macro. You can use either braces or parentheses to enclose MacroName.

MAKE expands macros at various times depending on where they appear in the makefile:

- Nested macros are expanded when the outer macro is invoked.
- Macros in rules and directives are expanded when MAKE first looks at the makefile.
- Macros in commands are expanded when the command is executed.

If MAKE finds an undefined macro in a makefile, it looks for an operating system environment variable of that name (usually defined with SET) and uses its definition as the expansion text. For example, if you wrote $(PATH) in a makefile and never defined PATH, MAKE would use the text you defined for PATH in your AUTOEXEC.BAT. See your operating system manuals for information on defining environment variables.
Syntax

<MacroName> = <expansion_text>

Element | Description
<MacroName> | Is case-sensitive (MACRO1 is different from Macro1). Limited to 512 characters.
<expansion_text> | Is limited to 4096 characters. Expansion characters may be alphanumeric, punctuation, or spaces.

You must define each macro on a separate line in your makefile and each macro definition must start on the first character of the line. For readability, macro definitions are usually put at the top of the makefile. If MAKE finds more than one definition of MacroName, the new definition overwrites the old one.

You can also define macros using the -D command-line option. No spaces are allowed before or after the equal sign (=); however, you can define more than one macro by separating the definitions with spaces. The following examples show macros defined at the command line:

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    make -Dsourcedir=c:\projecta
    make -Dcommand="bcc32 -c"
    make -Dcommand=bcc32 option=-c

Note: Macros defined in makefiles overwrite macros defined on the command line.

String Substitution in MAKE Macros

MAKE lets you temporarily substitute characters in a previously defined macro. For example, if you define the following macro:

SOURCE = f1.cpp f2.cpp f3.cpp

you can substitute the characters .obj for the characters .cpp by using the following MAKE command:

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    $(SOURCE:.cpp=.obj)

This substitution does not redefine the macro.

Rules for macro substitution:

- Syntax: $(MacroName:original_text=new_text)
- No space before or after the colon
- Characters in original_text must exactly match the characters in the macro definition (text is case-sensitive)

MAKE also lets you use macros within substitution macros. For example:
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    MYEXT=.C
    SOURCE=f1.cpp f2.cpp f3.cpp
    $(SOURCE:.cpp=$(MYEXT)) #Changes 'f1.cpp' to 'f1.C', etc.

The caret (^) symbol causes MAKE to interpret the next character literally. This is useful for inserting a new-line character. For example:

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    MYEXT=.C
    SOURCE=f1.cpp f2.cpp f3.cpp
    ($(SOURCE):.cpp=$(MYEXT)^
    )         # changes 'f1.cpp f2.cpp f3.cpp' to:
            # f1.C
            # f2.C
            # f3.C

Here, the caret tells MAKE to change each occurrence of .cpp to .C followed by the new-line character.

You can use this to create explicit rules that generate response files for TLIB.EXE. For example:

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    myfile.lib: file1.obj file2.obj file3.obj
    TLIB $@ @&&!
    +-$(**: = &^
    +-)
    !

Here, MAKE substitutes all space characters in the dependency list with a space followed by an ampersand (&) followed by the new-line character followed by "+-". The resulting response file looks like this:

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    +-file1.obj &
     +-file2.obj &
     +-file3.obj &
     +-

Default MAKE Macros

MAKE contains several default macros you can use in your makefiles. The following table lists the macro definition and what it expands to in explicit and implicit rules.

Macro | Expands in Implicit Rule | Expands in Explicit Rule
$* | path\dependent file | path\target file
$< | path\dependent file+ext | path\target file+ext
$: | path for dependents | path for target
$. | dependent file+ext | target file + ext
$& | dependent file | target file
$** | path\dependent file+ext | all dependents file+ext
$? | path\dependent file+ext | old dependents

Macro | Expands to | Comment
_ _MSDOS_ _ | 1 | If running under DOS
_ _MAKE_ _ | 0x0370 | MAKE's hex version number
MAKE | make | MAKE's executable file name
MAKEFLAGS | options | The options typed on the command line
MAKEDIR | directory | Directory where MAKE.EXE is located

Modifying Default MAKE Macros

If the default macros don't give you the exact string you want, macro modifiers let you extract parts of the string to suit your purpose. Macro modifiers are usually used with $< or $@.

To modify a default macro, use this syntax:

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    $(MacroName [modifier])

The following table lists macro modifiers and provides examples of their use:

Modifier | Part of File Name Expanded | Example | Result
D | Drive and directory | $(<D) | C:\PROJECTA\
F | Base and extension | $(<F) | MYSOURCE.C
B | Base only | $(<B) | MYSOURCE
R | Drive, directory, and base | $(<R) | C:\PROJA\SOURCE

See Also

Using MAKE.EXE

MAKE Directives

MAKE Rules and Commands

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